View W632GU8KB15I_8868382.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w632gu8kb 32 m ? ? publication release date: jan. 20 , 2015 revision: a05 - 1 - table of contents - 1. general description ................................ ................................ ................................ ................... 5 2. features ................................ ................................ ................................ ................................ ........... 5 3. order informati on ................................ ................................ ................................ ....................... 6 4. key parameters ................................ ................................ ................................ ............................. 7 5. ball configuration ................................ ................................ ................................ ...................... 8 6. ball description ................................ ................................ ................................ ............................ 9 7. block diagram ................................ ................................ ................................ .............................. 11 8. functional description ................................ ................................ ................................ ............ 12 8. 1 basic functionality ................................ ................................ ................................ .............................. 12 8.2 reset and initialization procedure ................................ ................................ ................................ .... 12 8.2.1 power - up initialization sequence ................................ ................................ ..................... 12 8.2.2 reset initialization with stable power ................................ ................................ .............. 14 8.3 programming the mode registers ................................ ................................ ................................ ....... 15 8.3.1 mode register mr0 ................................ ................................ ................................ ......... 17 8.3.1.1 burst length, type and order ................................ ................................ ................ 17 8.3.1.2 cas latency ................................ ................................ ................................ ........... 18 8.3.1.3 test mode ................................ ................................ ................................ ............... 18 8.3.1.4 dll reset ................................ ................................ ................................ ............... 18 8.3.1.5 write recovery ................................ ................................ ................................ ....... 19 8.3.1. 6 precharge pd dll ................................ ................................ ................................ . 19 8.3.2 mode register mr1 ................................ ................................ ................................ ......... 19 8.3.2.1 dll enable/disable ................................ ................................ ................................ 20 8. 3.2.2 output driver impedance control ................................ ................................ ........... 20 8.3.2.3 odt r tt values ................................ ................................ ................................ .... 20 8.3.2. 4 additive latency (al) ................................ ................................ ............................. 20 8.3.2.5 write levelin g ................................ ................................ ................................ .......... 20 8.3.2.6 output disable ................................ ................................ ................................ ........ 21 8.3.2. 7 tdqs, tdqs# ................................ ................................ ................................ ........ 21 8.3.3 mode register mr2 ................................ ................................ ................................ ......... 22 8.3.3.1 partial array self refresh (pasr) ................................ ................................ .......... 23 8.3.3.2 cas write latency (cwl) ................................ ................................ ...................... 23 8.3.3.3 auto self refresh (asr) and self refresh temperature (srt) ............................. 23 8.3.3.4 dynamic odt (rtt_wr) ................................ ................................ ......................... 23 8.3.4 mode register mr3 ................................ ................................ ................................ ......... 24 8.3.4.1 multi purpose register (mpr) ................................ ................................ ................ 24 8.4 no operation (nop) command ................................ ................................ ................................ .......... 25 8.5 deselect command ................................ ................................ ................................ ............................. 25 8.6 dll - off mode ................................ ................................ ................................ ................................ ...... 25 8.7 dll on/off switching procedure ................................ ................................ ................................ ........... 26 8.7.1 dll on to dll off procedure ................................ ................................ .......... 26 8.7.2 dll off to dll on procedure ................................ ................................ .......... 27 8.8 input clock frequency change ................................ ................................ ................................ .............. 28 8.8.1 frequency change during self - refresh ................................ ................................ ............ 28 8.8.2 frequency change during precharge power - down ................................ .......................... 28
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 2 - 8.9 write leveling ................................ ................................ ................................ ................................ ..... 30 8.9.1 dram setting for write leveling & dram termination function in that mode .................... 31 8.9.2 write leveling procedure ................................ ................................ ................................ . 31 8.9.3 write leveling mode exit ................................ ................................ ................................ . 33 8.10 multi purpose register ................................ ................................ ................................ ........................ 34 8.10.1 mpr functional description ................................ ................................ ............................. 35 8.10.2 mpr register address definition ................................ ................................ ..................... 36 8.10.3 relevant timing parameters ................................ ................................ ............................ 36 8.10.4 protocol example ................................ ................................ ................................ ............. 36 8.11 active command ................................ ................................ ................................ .............................. 42 8.12 precharge command ................................ ................................ ................................ .................... 42 8.13 read operation ................................ ................................ ................................ ................................ . 43 8.13.1 read burst operation ................................ ................................ ................................ ..... 43 8.13.2 read timing definitions ................................ ................................ ................................ .. 44 8.13.2.1 read timing; clock to data strobe relationshi p ................................ .................... 45 8.13.2.2 read timing; data strobe to data relationship ................................ ..................... 46 8.13.2.3 tlz(dqs), tlz(dq), thz(dqs), thz(dq) calculation ................................ ............. 47 8.13.2.4 trpre calculation ................................ ................................ ................................ .. 48 8.13.2.5 trp st calculation ................................ ................................ ................................ .. 48 8.13.2.6 burst read operation followed by a precharge ................................ ...................... 54 8.14 write operation ................................ ................................ ................................ ................................ 56 8.14.1 ddr3l burst operation ................................ ................................ ................................ ... 56 8.14.2 write timing violations ................................ ................................ ................................ . 56 8.14.2.1 motivation ................................ ................................ ................................ ............... 56 8.14.2.2 data setup and hold violations ................................ ................................ .............. 56 8.14.2.3 strobe to strobe and strobe to clock violations ................................ ..................... 56 8.14.2.4 write timing parameters ................................ ................................ ........................ 56 8.14.3 write data mask ................................ ................................ ................................ ............... 57 8.14.4 twpre calculation ................................ ................................ ................................ ........... 58 8.14 .5 twpst calculation ................................ ................................ ................................ ........... 58 8.15 refresh command ................................ ................................ ................................ .............................. 65 8.16 self - refresh operation ................................ ................................ ................................ ....................... 67 8.17 power - down modes ................................ ................................ ................................ ............................ 69 8.17.1 power - down entry and exit ................................ ................................ ............................. 69 8.17.2 power - down clarifications - case 1 ................................ ................................ ................. 75 8.17.3 power - down clarifications - case 2 ................................ ................................ ................. 75 8.17.4 power - down clarifications - case 3 ................................ ................................ ................. 76 8.18 zq calibration commands ................................ ................................ ................................ .................. 77 8.18.1 zq calibration description ................................ ................................ ............................... 77 8.18.2 zq calibration timing ................................ ................................ ................................ ...... 78 8.18.3 zq external resistor value, tolerance, and capacitive loading ................................ ...... 78 8.19 on - die termination (odt) ................................ ................................ ................................ .................. 79 8.19.1 odt mode register and odt truth table ................................ ................................ ...... 79 8.19.2 synchronous odt mode ................................ ................................ ................................ .. 80 8.19.2.1 odt latency and posted odt ................................ ................................ ............... 80 8.19.2.2 timing parameters ................................ ................................ ................................ . 80 8. 19.2.3 odt during reads ................................ ................................ ................................ .. 82 8.19.3 dynamic odt ................................ ................................ ................................ .................. 83 8.19.3.1 functional description: ................................ ................................ ........................... 83
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 3 - 8.19.3.2 odt timing diagrams ................................ ................................ ............................ 84 8.19.4 asynchronous odt mode ................................ ................................ ................................ 88 8.19.4.1 synchronous to asynchronous odt mode transitions ................................ .......... 89 8.19.4.2 synchronous to asynchronous odt mode transition during powe r - down entry .. 89 8.19.4.3 asynchronous to synchronous odt mode transition during power - down exit ..... 92 8.19.4.4 asynchronous to synchronous odt mode during short cke high and short cke low periods 93 9. operation mode ................................ ................................ ................................ ........................... 94 9.1 command truth table ................................ ................................ ................................ ........................ 94 9.2 cke truth table ................................ ................................ ................................ ................................ . 96 9.3 simplified state diagram ................................ ................................ ................................ ..................... 97 10. electrical characteristics ................................ ................................ ................................ ... 98 10.1 absolute maximum ratings ................................ ................................ ................................ ................ 98 10.2 operating temperature condition ................................ ................................ ................................ ....... 98 10.3 dc & ac operating conditions ................................ ................................ ................................ ........... 98 10.3.1 recommended dc operating conditions ................................ ................................ ........ 98 10.4 input and output leakage currents ................................ ................................ ................................ .... 99 10.5 interface test conditions ................................ ................................ ................................ .................... 99 10.6 dc and ac input measurement levels ................................ ................................ ............................. 100 10.6.1 dc and ac input levels for single - ended command and address signals .................. 100 10.6.2 dc and ac input levels for single - ended data signals ................................ ................ 100 10.6.3 differential swing requirements for clock (ck - ck#) and strobe (dqs - dqs#) ........... 102 10.6.4 single - ended requirements for differential signals ................................ ......................... 103 10.6.5 diffe rential input cross point voltage ................................ ................................ ............ 104 10.6.6 slew rate definitions for single - ended input signals ................................ .................... 105 10.6.7 slew rate definitions for differential input signals ................................ ........................ 105 10.7 dc and ac output measurement levels ................................ ................................ .......................... 106 10.7.1 output slew rate definition and requirements ................................ ............................. 106 10.7.1.1 single ended output slew rate ................................ ................................ ........... 107 10.7.1.2 differential output slew rate ................................ ................................ ............... 108 10.8 34 ohm output driver dc electrical characteristics ................................ ................................ ......... 109 10.8.1 output driver temperature and voltage sensitivity ................................ ........................ 111 10.9 on - die termination (odt) levels and characteristics ................................ ................................ ..... 112 10.9.1 odt levels and i - v characterist ics ................................ ................................ ............... 112 10.9.2 odt dc electrical characteristics ................................ ................................ ................. 113 10.9.3 odt temperature and voltage sensitivity ................................ ................................ ..... 113 10.9.4 design guide lines for rtt pu and rtt pd ................................ ................................ ....... 114 10.10 odt timing definitions ................................ ................................ ................................ ............ 115 10.10.1 test load for odt timings ................................ ................................ ............................ 115 10.10.2 odt timing definitions ................................ ................................ ................................ .. 115 10.11 input/output capacitance ................................ ................................ ................................ ........ 119 10.12 overshoot and undershoot specifications ................................ ................................ ............... 120 10.12.1 ac overshoot /undershoot specification for address and control pins: ....................... 120 10.12.2 ac overshoot /undershoot specification for clock, data, strobe and mask pins: ......... 120 10.13 idd and iddq specification parameters and test conditions ................................ ................ 121 10.13.1 idd and iddq measurement conditions ................................ ................................ ....... 121 10.13.2 idd current specifications ................................ ................................ ............................. 131 10.14 clock specification ................................ ................................ ................................ .................. 132 10 .15 speed bins ................................ ................................ ................................ .............................. 133 10.15.1 ddr3l - 1333 speed bin and operating conditions ................................ ....................... 133
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 4 - 10.15.2 ddr3l - 1600 speed bin and operating conditions ................................ ....................... 134 10.15.3 ddr3l - 1866 speed bin and operating conditions ................................ ....................... 135 10.15.4 speed bin general notes ................................ ................................ .............................. 136 10.16 ac characteristics ................................ ................................ ................................ ................... 137 10.16.1 ac timing and operating condition for - 11 speed grade ................................ .............. 137 10.16.2 ac timing and operating condition for - 12/12i/ - 15/15i speed grades ........................... 141 10.16.3 timing parameter notes ................................ ................................ ................................ 145 10.16.4 address / command setup, hold and derating ................................ ............................. 148 10.16.5 data setup, hold and slew rate derating ................................ ................................ ..... 155 11. backward compatible to 1.5v ddr3 sdram vdd/vddq requirements ................................ ....... 157 11.1 input/output functional ................................ ................................ ................................ ..................... 157 11.2 recommended dc operating conditions - ddr3l (1.35v) operation ................................ .............. 157 11.3 recommended dc operating conditions - ddr3 (1.5v) o peration ................................ .................. 157 11.4 vddq/vddq voltage switch between ddr3l and ddr3 ................................ ............................... 157 12. package specification ................................ ................................ ................................ ............ 159 13 . revision history ................................ ................................ ................................ ........................ 160
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 5 - 1. general description the w632gu8kb is a 2 g b its ddr3l s dram , organized as 33,554,432 words ? 8 banks ? 8 bits. this device achieves high speed transfer rates up to 1 866 mb/sec/pin (ddr 3l - 1 866 ) for various applications. the w632gu8kb is sorted into the following speed grades: - 11, - 12, 12i, - 15 and 15i . the - 11 speed grade is compliant to the ddr 3l - 1866 ( 13 - 13 - 13 ) specification . the - 12 and 12i speed grade s are compliant to the ddr3l - 1600 (11 - 11 - 11) specification ( the 12 i industrial grade which is guaranteed to support - 4 0 c t case 9 5 c ) . t he - 15 and 15i speed grade s are compliant to the ddr3l - 1333 (9 - 9 - 9) specification ( the 15 i industrial grade which is guaranteed to support - 4 0 c t case 9 5 c ) . the w632gu8kb is designed to comply with the following key ddr3l sdram features such as posted cas# , p rogrammable cas# write latency (cwl), zq calibration, o n d ie t ermination and a synchronous r eset. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of diffe rential clocks ( ck rising and ck# falling). all i/os are synchronized with a differential dqs - dqs# pair in a source synchronous fashion. 2. feat ures ? power supply: 1.35v (typ.) , v dd , v ddq = 1.283v to 1.45v ? backward compatible to v dd , v ddq = 1.5v 0.075v ? double data rate architecture: two data transfers per clock cycle ? eight internal banks for concurrent operation ? 8 bit prefetch architecture ? cas latency: 6, 7, 8, 9, 10, 11 and 13 ? burst length 8 (bl8) and burst chop 4 (bc4) modes: fixed via mode register (mrs) or selectable on - the - fly (otf) ? programmable read burst ordering: interleaved or nibble sequential ? bi - directional, differential data strobes (dqs and dqs# ) are transmitted / received with data ? edge - aligned with r ead data and center - aligned with w rite data ? dll aligns dq and dqs transitions with clock ? differential clock inputs ( ck and ck# ) ? commands entered on each positive ck edge , d ata a nd data mask are referenced to both edges of a differential data strobe pair (double data rate) ? posted cas with programmable additive latency (al = 0, cl - 1 and cl - 2) for improved command, address and data bus efficiency ? read latency = additive latency plus cas latency (rl = al + cl) ? auto - precharge operation for read and write bursts ? refresh, self - refresh , auto self - refresh (asr) and partial array self refresh (pasr) ? precharged power down and active power down ? data masks (dm) for write data ? programmable cas write latency (cwl) per operating frequency ? write latency wl = al + cwl ? multi purpose register (mpr) for readout a predefined system timing calibration bit sequence
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 6 - ? system level timing calibration support via write leveling and mpr read pattern ? zq calibration for output driver and odt using external reference resistor to ground ? asynchronous reset # pin for power - up i nitialization s equence and reset function ? programmable on - die termination (odt) for data, data mask and differential strobe pairs ? dynami c odt mode for improved signal integrity and preselectable termination impedances during writes ? 1 k byte page size ? packaged in w bga 78 ball ( 8 x 1 0.5 mm 2 ) , using l ead free materials with rohs compliant 3. order information part number speed grade operating temperature w63 2 gu8kb - 1 1 ddr 3l - 1 866 ( 13 - 13 - 13 ) 0c t case 9 5c w632gu8kb - 1 2 ddr3l - 1 600 ( 11 - 11 - 11 ) 0c t case 9 5c w632gu8kb 12i ddr3l - 1 600 ( 11 - 11 - 11 ) - 4 0c t case 9 5c w632gu8kb - 1 5 ddr3l - 1333 ( 9 - 9 - 9 ) 0c t case 9 5c w632gu8kb 1 5 i ddr3l - 1333 ( 9 - 9 - 9 ) - 4 0c t case 9 5c
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 7 - 4. key parameters speed bin ddr3 l - 1 866 ddr3 l - 1 600 ddr3 l - 1 333 unit cl - nrcd - nrp 13 - 13 - 13 11 - 11 - 11 9 - 9 - 9 part number exten s ion - 11 - 12 /12i - 15 /15i parameter sym . m in . m ax . m in . m ax . m in . m ax . maximum operating frequency using maximum allowed settings for sup_cl and sup_cwl f ckmax ? 933 ? 800 ? 667 mhz internal read command to first data t aa 13.91 20 13. 7 5 (13.125) * 5 20 13.5 (13.125) * 5 20 ns act to internal read or write delay time t rcd 13.91 ? 13. 7 5 (13.125) * 5 ? 13.5 (13.125) * 5 ? ns pre command period t rp 13.91 ? 13. 7 5 (13.125) * 5 ? 13.5 (13.125) * 5 ? ns act to act or ref command period t rc 47.91 ? 48 . 7 5 ( 48 .125) * 5 ? 49 .5 ( 49 .125) * 5 ? ns act to pre command period t ras 34 9 * t refi 35 9 * t refi 36 9 * t refi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 ns cl = 7 cwl = 6 t ck(avg) reserved 1.875 < 2.5 1.875 < 2.5 ns cl = 8 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns cl = 9 cwl = 7 t ck(avg) reserved 1.5 < 1.875 1.5 < 1.875 ns cl = 10 cwl = 7 t ck(avg) 1.5 < 1.875 1.5 < 1.875 1.5 < 1.875 ns cl = 11 cwl = 8 t ck(avg) reserved 1.25 < 1.5 reserved ns cl = 13 cwl = 9 t ck(avg) 1.07 < 1.25 reserved reserved ns supported cl settings sup_cl 6, 8, 10, 13 6, ( 7 ) , 8, ( 9 ) , 10, 11 6, (7) , 8, 9, 10 nck supported c w l settings sup_cwl 5, 6, 7, 9 5, 6, 7, 8 5, 6, 7 nck average periodic refresh interval - 4 0c t cas e 85c t refi ? ? * 2 ? 7.8 * 2, 3 ? 7.8 * 2, 3 s 0c t cas e 85c ? 7.8 * 1 ? 7.8 * 1 ? 7.8 * 1 s 85 c < t cas e 9 5c ? 3 . 9 * 4 ? 3 . 9 * 4 ? 3 . 9 * 4 s operating one bank active - precharge current i dd0 ? 105 ? 95 ? 90 ma operating one bank active - read - precharge current i dd 1 ? 120 ? 115 ? 110 ma operating burst read current i dd4r ? 250 ? 220 ? 205 ma operating burst write current i dd4w ? 230 ? 200 ? 180 ma burst refresh current i dd5b ? 145 ? 140 ? 135 ma self - refresh current, t oper = 0 ~ 85c i dd6 ? 19 ? 19 ? 19 ma operating bank interleave current i dd7 ? 360 ? 340 ? 330 ma n ote s : ( field value contents in blue font or parentheses are optional ac parameter and cl setting ) 1. all speed grades s upport 0 c t cas e 85 c with full jedec ac and dc specifications . 2. for - 1 1 , - 12 and - 15 speed grade s , - 4 0 c t cas e < 0 c is not available . 3. 12i and 15i speed grade s s upport - 4 0 c t cas e 8 5 c with full jedec ac and dc specifications . 4. for all speed grade parts, t cas e is able to extend to 95c with doubling auto refresh commands in frequency to a 32 ms period ( t refi = 3.9 s) , it is mandatory to either use the manual self - refresh mode with extended temperature range capability (mr2 a6 = 0 b and mr2 a7 = 1 b ) or enable the auto self - refresh mode (asr) (mr2 a6 = 1 b , mr2 a7 is don't care ) . 5. for devices supporting optional down binning to cl=7 and cl=9, t aa /t rcd /t rp min must be 13.125 ns or lower. spd setti ngs must be programmed to match. for example, ddr3l - 1333 (9 - 9 - 9) devices supporting down binning to ddr3l - 1066 (7 - 7 - 7) should program 13.125 ns in spd bytes for t aa min (byte 16), t rcd min (byte 18), and t rp min (byte 20). ddr3l - 1600 (11 - 11 - 11) devices supporting down binning to ddr3l - 1333 (9 - 9 - 9) or ddr3l - 1066 (7 - 7 - 7) should program 13.125 ns in spd bytes for t aa min (byte16), t rcd min (byte 18), and t rp min (byte 20). once t rp (byte 20) is programmed to 13.125 ns, t rc min (byte 21, 23) also should be progr ammed accodingly. for example, 49.125n s (t ras min + t rp min = 36 n s + 13.125 n s ) for ddr3l - 1333 (9 - 9 - 9) and 48.125 ns (t ras min + t rp min = 35 ns + 13.125 ns) for ddr3l - 1600 (11 - 11 - 11) .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 8 - 5. ball configuration 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l n u / t d q s # m n d m / t d q s d q 1 v d d d q 7 c k c k # a 1 0 / a p n c a 1 2 / b c # a 1 a 1 1 a 1 4 a 8 a 6 a 4 b a 1 v r e f c a z q v d d v s s d q 5 v s s d q 3 v s s q v s s v d d v d d q v s s q v s s q v d d q n c c k e n c v s s v d d v s s v d d v s s n c d q 0 d q s d q s # d q 4 r a s # c a s # w e # b a 2 a 0 a 2 a 9 a 1 3 r e s e t # a 7 a 5 a 3 b a 0 c s # v d d v s s v d d q d q 6 d q 2 v s s q v d d v s s v s s v d d q v s s q v r e f d q n c o d t n c v s s v d d v s s v d d v s s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 9 - 6. ball description ball number symbol type description f 7, g 7 ck, ck# input clock: ck and ck# are differential clock inputs. all addres s and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck# . g9 cke input clock enable: cke high activates, and cke low deactiva tes, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power down and self - refresh operation (all banks idle), or active power down (row active in any bank). cke is asynchronous for self - refresh exit. after v refca and v refdq have become stable during the power on and initialization sequence, they must be maintained during all operations (including self - refresh). cke must be maintained high throughout read and write ac cesses. input buffers, excluding ck, ck# , odt and cke, are di sabled during power down. input buffers, excluding cke, are disabled during self - refresh. h2 cs# input chip select: all commands are masked when cs# is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. g1 odt input on die termination: odt (registered high) enables termination resistance internal to the ddr3l sdram. when enabled, odt is applied to each dq, dqs, dqs# and dm/tdqs, nu/tdqs# (when tdqs is enabled via mode register a11=1 in mr1) signal . t he odt signal will be ignored if mode registers mr1 and mr2 are programmed to disable odt and during self refresh . f 3, g 3, h 3 ras#, cas# , we# input command inputs: ras#, cas# and we# (along with cs#) define the command being entered. b7 dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. the function of dm or tdqs/tdqs# is enabled by mode register a11 setting in mr1 . j 2, k 8, j 3 ba0 ? ba2 input bank address inputs: ba0 ? ba2 define to which bank an active, read, write, or precharge command is being applied. bank address also determines which mode register is to be accessed during a mrs cycle. k 3, l 7, l 3, k 2, l 8, l 2, m 8, m 2, n 8, m 3, h 7, m 7, k 7 , n3, n7 a0 ? a1 4 input address input s: provide the row address for active commands a nd the column address for read/ write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc# have additional functions; see below). the address inputs also provide the op - code during mode register set command . row address: a0?a1 4 . column address: a0?a9. h7 a10/ ap input auto - precharge: a10 is sampled during read/write commands to determine whether auto - precharge should be performed to the accessed bank after the read/write operation. (high: auto - precharge ; low: no a uto - precharge ). a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. k7 a1 2 / bc# input burst chop: a12/ bc# is sampled during read and write commands to determine if burst chop (on - the - fly) will be performed. (high, no burst chop; low: burst chopped). see section 9 .1 command truth table on p age 9 4 for details. n2 reset# input active low asynchronous reset: reset is active when reset# is low, and inactive when reset# is high. reset# must be high during normal operation. reset# is a cmos rai to rail signal with dc high and low at 80% and 20% of v dd , reset# active is destructive to data contents .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 10 - b 3, c 7, c 2, c 8, e 3, e 8, d 2, e 7 dq0 ? dq7 input/output data input/ output: lower byte of bi - directional data bus. c 3, d 3 dqs, dqs# input/output d ata strobe: o utput with read data, input with write data. edge - aligned with read data, centered in write data. dqs is paired with dqs# to provide differential pair signaling to the system during read and write data transfer. ddr3l sdram supports differential data strobe only and does not support single - ended . b 7, a 7 tdqs, tdqs# output termination data strobe : when tdqs enabled via mode register a11 = 1 in mr1, the dram will enable the same termination resistance function on tdqs/t dqs# that is applied to dqs/dqs#. when tdqs disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask function and tdqs# is not used . a 2, a 9, d 7, g 2, g 8, k 1, k 9, m 1, m 9 v dd supply power supply: 1.283v to 1.45v operational . a 1 , a8 , b 1, d 8, f 2, f 8, j 1, j 9, l 1, l 9, n 1, n 9 v ss supply ground . b9 , c1 , e2 , e 9 v ddq supply dq power supply: 1.283v to 1.45v operational . b 2 , b 8 , c9 , d 1 , d9 v ssq supply dq ground . e1 v ref dq supply reference voltage for dq . j8 v ref ca supply reference v oltage for control, command and address inputs . h8 zq supply external reference ball for output drive and on - die termination impedance calibration : this ball n eeds an external 240 1% external resist or (rzq), connected from this ball to ground to perform zq calibration . a3 , f1 , f9 , h1 , h9 , j 7 nc no connect: no internal electrical connection is present . n ote: input only ball s (ba0 - ba2, a0 - a1 4 , ras#, cas#, we#, cs#, cke, odt and reset#) do not supply termination.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 11 - 7. block diagram c k e a 1 0 c l o c k b u f f e r c o m m a n d d e c o d e r a d d r e s s b u f f e r r e f r e s h c o u n t e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r m o d e r e g i s t e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c o l u m n d e c o d e r s e n s e a m p l i f i e r d a t a c o n t r o l c i r c u i t d m m a s k l o g i c d q b u f f e r c o l u m n d e c o d e r s e n s e a m p l i f i e r n o t e : t h e c e l l a r r a y c o n f i g u r a t i o n i s 3 2 7 6 8 * 1 0 2 4 * 8 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r a 0 a 9 a 1 1 a 1 2 a 1 3 a 1 4 c s # r a s # c a s # w e # c k , c k # p r e f e t c h r e g i s t e r o d t c o n t r o l c o l u m n d e c o d e r s e n s e a m p l i f i e r c o l u m n d e c o d e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c o l u m n d e c o d e r c e l l a r r a y b a n k # 5 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r o d t c e l l a r r a y b a n k # 7 c e l l a r r a y b a n k # 4 c e l l a r r a y b a n k # 6 c e l l a r r a y b a n k # 3 c e l l a r r a y b a n k # 2 c e l l a r r a y b a n k # 1 z q c a l z q c l , z q c s r z q v s s q z q t o o d t / o u t p u t d r i v e r s b a 2 b a 1 b a 0 c o l u m n d e c o d e r s e n s e a m p l i f i e r r o w d e c o d e r c e l l a r r a y b a n k # 0 d l l c k , c k # w r i t e d r i v e r s r e a d d r i v e r s d q 0 ? d q 7 d q s , d q s # t d q s , t d q s # d q 0 ? d q 7 d q s , d q s # t d q s , t d q s # d m d m
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 12 - 8. functional descripti on 8.1 basic functionality the ddr3l sdram is a high - speed dynamic random - access memory internally configured as an eight - bank dram. the ddr3l sdram uses a n 8n prefetch architecture to achieve high - speed operation. the 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write operation for the ddr3l sdr am consists of a single 8n - bit wide, four clock data transfer at the internal dram core and eight corresponding n - bit wide, one - half clock cycle data transfers at the i/o pins . read and write operation to the ddr3l sdram are burst oriented, start at a sele cted location, and continue for a burst length of eight or a chopped burst of four in a programmed sequence. operation begins with the registration of an active command, which is then followed by a read or write command. the address bits registered coinc ident with the active command are used to select the bank and row to be activated (ba0 - ba2 select the bank; a0 - a14 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for th e burst operation, determine if the auto precharge command is to be issued (via a10), and select bc4 or bl8 mode on the fly (via a12) if enabled in the mode register. prior to normal operation, the ddr3l sdram must be powered up and initialized in a pred efined manner. the following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation. 8.2 reset and initialization procedure 8.2.1 power - up initialization sequence the following sequence is required for power up and initialization . 1. apply power (reset# is recommended to be maintained below 0.2 * v dd ; all other inputs may be undefined). reset# needs to be maintained for minimum 200 s with stable power. cke is pulled low anytime b efore reset# being de - asserted (min. time 10 n s ). the power voltage ramp time between 300 m v to v dd min . must be no greater than 200 m s ; and during the ramp, v dd v ddq and ( v dd - v ddq ) < 0.3 v olts. ? v dd and v ddq are driven from a single power converter out put, and ? the voltage levels on all pins other than v dd , v ddq , v ss , v ssq must be less than or equal to v ddq and v dd on one side and must be larger than or equal to v ssq and v ss on the other side. in addition, v tt is limited to 0.95 v max once power ramp is finished, and ? v ref tracks v ddq /2. or ? apply v dd without any slope reversal before or at the same time as v ddq . ? apply v ddq without any slope reversal before or at the same time as v tt & v ref . ? the voltage levels on all pins other than v dd , v ddq , v ss , v ssq must be less than or equal to v ddq and v dd on one side and must be larger than or equal to v ssq and v ss on the other side. 2. after reset# is de - asserted, wait for another 500 s until cke becomes active. during this time, the dram will start internal state initialization; this will be done independently of external clocks. 3. clocks (ck, ck#) need to be started and stabilized for at least 10 n s or 5 t ck (which is larger) before cke goes active. since cke is a synchronous signal, the correspondi ng set up time to clock (t is ) must be met. also, a nop or deselect command must be registered (with t is set up time to clock) before cke goes active. once the cke is registered high after reset, cke needs to be continuously regist ered high until the initialization sequence is finished, including expiration of t dllk and t zq init.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 13 - 4. the ddr3l sdram keeps its on - die termination in high - imped ance state as long as reset# is asserted. further, the sdram keeps its on - die termination in hi gh impedance state after reset# deassertion until cke is registered high. the odt input signal may be in undefined state until t is before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high . if r tt _n om is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input signal remains static until the power up initialization sequence is finished, including the expiration of t dllk and t zq init . 5. after cke is be ing registered high, wait minimum of reset cke exit time, t xpr , before issuing the first mrs command to load mode register. (t xpr =max (t xs ; 5 * t ck ) 6. issue mrs command to load mr2 with all application settings. (to issue mrs command for mr2, provide low to ba0 and ba2, high to ba1.) 7. issue mrs command to load mr3 with all application settings. (to issue mrs command for mr3, provide low to ba2, high to ba0 and ba1.) 8. issue mrs command to load mr1 with all application settings and dll enabled. (to issue dll enable command, provide low to a0, high to ba0 and low to ba1 - ba2). 9. issue mrs command to load mr0 with all application settings and dll reset. (to issue dll reset command, provide high to a8 and low to ba0 - 2). 10. issue zqcl command to start ing zq calibration. 11. wait for both t dllk and t zq init completed. 12. the ddr3l sdram is now ready for normal operation . n ote : 1 . from time point td until tk nop or des commands must be applied between mrs and zqcl commands. figure 1 C reset and initialization sequence at power - on ramping t i m e b r e a k d o n ' t c a r e t a t b t c t d t e t f t g t h t i t j t k c k , c k # v d d , v d d q r e s e t # c o m m a n d b a o d t r t t t c k s r x t = 2 0 0 s t = 5 0 0 s t d l l k v a l i d v a l i d v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g . o t h e r w i s e s t a t i c h i g h o r l o w * 1 z q c l m r s * 1 m r s m r s m r s m r 2 m r 3 m r 1 m r 0 t i s t i s t i s t i s t x p r t m r d t m r d t m r d t m o d t z q i n i t t m i n c k e 1 0 n s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 14 - 8.2.2 reset initialization with stable power the following sequence is required for reset at no power interruption initialization . 1. asserted reset below 0.2 * v dd anytime when reset is needed (all other inputs may be undefined). reset needs to be maintained for minimum 100 n s . cke is pulled low before reset being de - asserted (min. time 10 n s ). 2. follow power - up initialization sequence steps 2 to 11 . 3. the reset sequence is now completed; ddr3l sdram is ready for normal operation. n ote : 1 . from time point td until tk nop or des commands must be applied between mrs and zqcl commands . figure 2 C reset procedure at power stable condition t i m e b r e a k d o n ' t c a r e t a t b t c t d t e t f t g t h t i t j t k c k , c k # v d d , v d d q r e s e t # c o m m a n d b a o d t r t t t c k s r x t = 1 0 0 n s t = 5 0 0 s t d l l k v a l i d v a l i d v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g . o t h e r w i s e s t a t i c h i g h o r l o w * 1 z q c l m r s * 1 m r s m r s m r s m r 2 m r 3 m r 1 m r 0 t i s t i s t i s t i s t x p r t m r d t m r d t m r d t m o d t z q i n i t t m i n = 1 0 n s c k e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 15 - 8.3 programming the mode registers for application flexibility, various functions, features, and modes are programmable in four mode registers, provided by the ddr3l sdram, as user defined variables and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, contents of mode registers must be fully initialized and/or re - initialized, i.e., written, after power up and/or reset for proper operation. also the contents of the mode registers can be altered by re - ex ecuting the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub - set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs comm and is issued . mrs command and dll res et do not affect array contents, which mean these commands can be executed any time after power - up without affecting the array contents . the mode register set command cycle time, t mrd is required to complete the write operation to the mode register and is the minimum time required between two mrs commands shown in figure 3 . figure 3 C t mrd timing t i m e b r e a k d o n ' t c a r e t 0 t 1 t 2 t a 0 t a 1 t b 0 t b 1 t b 2 t c 0 t c 1 t c 2 c k # c k c o m m a n d o d t c k e v a l i d a d d r e s s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d n o p / d e s n o p / d e s m r s n o p / d e s n o p / d e s m r s v a l i d o d t s e t t i n g s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d o l d s e t t i n g s u p d a t i n g s e t t i n g s n e w s e t t i n g s t m r d t m o d o d t l o f f + 1 r t t _ n o m d i s a b l e d p r i o r a n d / o r a f t e r m r s c o m m a n d r t t _ n o m e n a b l e d p r i o r a n d / o r a f t e r m r s c o m m a n d
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 16 - the mrs command to non - mrs command delay , t m o d is required for the dram to update the features, except dll reset, and is the minimum time required from a mrs command to a non - mrs command excluding nop and des shown in figure 4 . figure 4 C t m o d timing the mode register contents can be changed using the same command and timing requirements during normal operation as long as the dram is in idle state, i.e., all banks are in the precharged state with t rp satisfied, all data bursts are completed and cke is high prior to writing into the mode register. if the r tt _n om feature is enabled in the mod e register prior and/or after a mrs c ommand, the odt s ignal must continuously be registered low ensuring r tt is in an off s tate prior to the mrs command. the odt s ignal may be registered high after t mod has expired. if the r tt _n om f eature is disabled in the mode register prior and after a mrs command, the odt s ignal can be registered either low or high before, during and after the mrs command. the mode registers are divided into various fields depending on the functionality and/or modes . t i m e b r e a k d o n ' t c a r e t 0 t 1 t 2 t a 0 t a 1 t a 2 t a 3 t a 4 t b 0 t b 1 t b 2 c k # c k c o m m a n d o d t c k e v a l i d a d d r e s s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d n o p / d e s n o p / d e s n o p / d e s n o p / d e s n o p / d e s m r s v a l i d o d t s e t t i n g s v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d o l d s e t t i n g s u p d a t i n g s e t t i n g s n e w s e t t i n g s t m o d r t t _ n o m e n a b l e d p r i o r a n d / o r a f t e r m r s c o m m a n d r t t _ n o m d i s a b l e d p r i o r a n d / o r a f t e r m r s c o m m a n d o d t l o f f + 1
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 17 - 8.3.1 mode register mr0 the mode register mr0 stores the data for controlling various operating modes of ddr3l sdram. it controls burst length, read burst type, cas latency, test mode, dll reset, wr and dll control for precharge power down, which include variou s vendor specific options to make ddr3l sdram useful for various applications. the mode register is written by asserting low on cs # , ras # , cas # , we # , ba0, ba1 and ba2, while controlling the states of address pins according to the figure 5 below . note s : 1. ba2 , a13 and a1 4 are reserved for future use and must be programmed to 0 during mrs. 2. wr (write recovery for a uto precharge)min in clock cycles is calculated by dividing t wr (in n s ) by t ck (in n s ) and rounding up to the next integer: wrmin[cycles] = roundup(t wr [n s ] / t ck (avg) [n s ]). the wr value in the mode register must be programmed to be equal or larger than wrmin. the programmed wr value is used with t rp to determine t dal . 3. the table only shows the encodings for a give n cas latency. for actual supported c as latency, please refer to speed bins tables for each frequency . 4. the table only shows the encodings for write recovery. for actual write recovery timing, please refer to ac timing table. figure 5 C mr0 definition 8.3.1.1 burst length, type and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in figure 5 . the ordering of accesses within a burst is determined by the burst length, burst type, and the st arting column address as shown in table 1 . the burst length is defined by bits a0 - a1. burst length options include fixed bc4, fixed bl8 and on the fly which allows bc4 or bl8 to be selected coincident with the registration of a read or write command via a12/bc # . l a t e n c y a 2 a 4 a 5 a 6 w r ( c y c l e s ) a 9 a 1 0 a 1 1 a 1 2 d l l r e s e t a 8 b a 1 b a 0 m r s m o d e b l a 0 a 1 r e a d b u r s t t y p e a 3 d l l c o n t r o l f o r p r e c h a r g e p d b a 0 a 1 4 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 * 1 p p d w r d l l r b t c l b l t m 0 1 n o y e s 0 0 0 1 1 0 1 1 m r 0 m r 1 m r 2 m r 3 1 0 s l o w e x i t ( d l l o f f ) f a s t e x i t ( d l l o n ) b u r s t l e n g t h a d d r e s s f i e l d m o d e r e g i s t e r 0 w r i t e r e c o v e r y f o r a u t o p r e c h a r g e c a s l a t e n c y 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 r e s e r v e d 7 8 9 1 1 1 0 r e s e r v e d 6 0 0 0 1 8 ( f i x e d ) b c 4 o r 8 ( o n t h e f l y ) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 1 6 * 2 5 * 2 6 * 2 7 * 2 8 * 2 1 0 * 2 1 4 * 2 1 2 * 2 a 7 m o d e 0 1 n o r m a l t e s t 0 1 n i b b l e s e q u e n t i a l i n t e r l e a v e 0 a 1 3 c l 0 0 0 0 1 1 1 1 1 1 0 1 b c 4 ( f i x e d ) r e s e r v e d b a 1 0 0 1 0 0 0 1 1 1 1 r e s e r v e d r e s e r v e d 1 3 0 0 0 0 1 0 1 1 1 r e s e r v e d r e s e r v e d 1 0 0 1 1 1 1 0 1 1 1 r e s e r v e d r e s e r v e d r e s e r v e d 1 1 1 b a 2 0 * 1
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 18 - table 1 C burst type and burst order burst length read/ write starting column address (a2, a1, a0) burst type = sequential (decimal) a3 = 0 burst type = interleaved (decimal) a3 = 1 notes 4 chop read 0 0 0 0,1,2,3,t,t,t,t 0,1,2,3,t,t,t,t 1, 2, 3 0 0 1 1,2,3,0,t,t,t,t 1,0,3,2,t,t,t,t 1, 2, 3 0 1 0 2,3,0,1,t,t,t,t 2,3,0,1,t,t,t,t 1, 2, 3 0 1 1 3,0,1,2,t,t,t,t 3,2,1,0,t,t,t,t 1, 2, 3 1 0 0 4,5,6,7,t,t,t,t 4,5,6,7,t,t,t,t 1, 2, 3 1 0 1 5,6,7,4,t,t,t,t 5,4,7,6,t,t,t,t 1, 2, 3 1 1 0 6,7,4,5,t,t,t,t 6,7,4,5,t,t,t,t 1, 2, 3 1 1 1 7,4,5,6,t,t,t,t 7,6,5,4,t,t,t,t 1, 2, 3 write 0,v,v 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 1, 2, 4, 5 1 ,v,v 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 1, 2, 4, 5 8 read 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2 0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2 0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 2 0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 2 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 2 1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 2 1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 2 1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 2 write v,v,v 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2, 4 note s : 1. in case of burst length being fixed to 4 by mr0 setting, the internal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for t wr and t wtr will be pulled in by two clocks. in case of burst length being selected on - the - fly via a12/bc#, the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on - the - f ly control, the starting point for t wr and t wtr will not be pulled in by two clocks . 2. 0...7 bit number is value of ca[2:0] that causes this bit to be the first read during a burst . 3. t: output driver for data and strobes are in high impedance . 4. v: a valid logi c level (0 or 1), but respective buffer input ignores level on input pins . 5. x: d on't c are . 8.3.1.2 cas latency the cas latency is defined by mr0 ( bits a2, a4, a5 and a6 ) as shown in figure 5 . cas latency is the delay, in clock cycles, between the internal read comm and and the availability of the first bit of output data. ddr3l sdram does not support any half - clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. for more information on the supported cl and al settings based on the operating clock frequency , refer to section 10 .1 5 speed bins on page 1 3 3 . for detailed read operation refer to section 8 .1 3 read operation on page 4 3 . 8.3.1.3 test mode the normal operating mode is selected by mr0 (bit a7 = 0) and all other bits set to the desired values sho wn in figure 5 . programming bit a7 to a 1 places the ddr3l sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is specified if a7 = 1. 8.3.1.4 dll reset the dll reset bit is self - clearing, meaning that it returns back to the value of 0 after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset should be applied. any time that the dll reset function is used, t dllk must be met before any functions that requ ire the dll can be used (i.e., read commands or odt synchronous operations) .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 19 - 8.3.1.5 write recovery the programmed wr value mr0 (bits a9, a10 and a11) is used for the auto precharge feature along with t rp to determine t dal . wr (write recovery for auto - precharge) min in clock cycles is calculated by dividing t wr (in n s ) by t ck (avg) (in n s ) and rounding up to the next integer: wrmin[cycles] = roundup (t wr [n s ]/t ck (avg) [n s ]). the wr must be programmed to be equal to or larger than t wr (min). 8.3.1.6 precharge pd dll mr0 (bit a1 2) is used to select the dll usage during precharge power down mode. when mr0 (a12 = 0), or slow - exit, the dll is frozen after entering precharge power down (for potential power savings) and upon exit requires t xpdll to be met prior to the next valid command. when mr0 (a12 = 1), or fast - exit, the dll is maintained after entering precharge power down and upon exiting power down requires t xp to be met prior to the next valid command. 8.3.2 mode register mr1 the mode registe r mr1 stores the data for enabling or disabling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is written by asserting low on cs#, ras#, cas#, we#, high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to the figure 6 below . note s : 1. ba2, a8 , a10, a13 and a1 4 are reserved for future use and must be programmed to 0 during mrs . 2. outputs disabled - dqs, dqss, dqs#s . 3. in write leveling mode (mr1 a [7] = 1) with mr1 a [12]=1, all r tt _nom settings are allowed; in write leveling mode (mr1 a [7] = 1) with mr1 a [12]=0, only r tt _nom settings of rzq/2, rzq/4 and rzq/6 are allowed . 4. if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed . figure 6 C mr 1 definition b a 1 b a 0 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 * 1 r t t _ n o m r t t _ n o m a d d r e s s f i e l d m o d e r e g i s t e r 1 b a 1 b a 0 0 0 0 0 1 1 1 1 m r 0 m r 1 m r 2 m r 3 a l q o f f t d q s 0 * 1 r t t _ n o m d . i . c d l l 0 a 0 1 e n a b l e d i s a b l e r t t _ n o m d i s a b l e d r z q / 6 r z q / 1 2 * 4 r z q / 4 r z q / 2 a 9 a 6 a 2 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 o u t p u t b u f f e r e n a b l e d o u t p u t b u f f e r d i s a b l e d * 2 1 0 e n a b l e d d i s a b l e d a 1 4 a 1 3 0 1 1 0 d i s a b l e e n a b l e d . i . c l e v e l 0 * 1 0 0 1 1 0 1 0 1 0 ( a l d i s a b l e d ) r e s e r v e d c l - 1 c l - 2 r e s e r v e d r e s e r v e d r z q / 8 * 4 1 1 1 1 0 0 1 1 1 a 5 0 0 1 1 a 1 0 1 0 1 r z q / 6 r e s e r v e d r z q / 7 r e s e r v e d n o t e : r z q = 2 4 0 o h m s n o t e : r z q = 2 4 0 o h m s b a 2 0 * 1 m r s e l e c t r t t _ n o m * 3 d l l e n a b l e o u t p u t d r i v e r i m p e d a n c e c o n t r o l a 4 a 3 a d d i t i v e l a t e n c y q o f f * 2 t d q s e n a b l e w r i t e l e v e l i n g e n a b l e a 1 2 a 1 1 a 7
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 20 - 8.3.2.1 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll di sabled. during normal operation (dll - on) with mr1 (a0 = 0), the dll is automatically disabled when entering self refresh operation and is automatically re - enabled upon exit of self refresh operation. any time the dll is enabled and subsequently reset, t dll k clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t dqsck , t aon or t aof parameters. during t dllk , cke must continuously be registered high. ddr3l sdram does not require dll for any write operation , except when rtt_wr is enabled and the dll is required for proper odt operation. for more detailed information on dll disable operation refer to section 8 .6 dll - off mode on page 2 5 . the direct odt feature is not supported during dll - off mode. the on - die terminat ion resistors must be disabled by continuously registering the odt pin low and/or by programming the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. the dynamic odt feature is not supported at dll - off mode. user m ust use mrs command to set rtt_wr, mr2 {a10, a9} = {0,0}, to disable dynamic odt externally. 8.3.2.2 output driver impedance control the output driver impedance of the ddr3l sdram device is selected by mr1 (bits a1 and a5) as shown in figure 6 . 8.3.2.3 odt r tt values ddr3l sdram is capable of providing two different termination values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1. a separate value (rtt_wr) may be programmed in mr2 to enable a unique r tt value when odt is enabled durin g writes. the rtt_wr value can be applied during writes even when rtt_nom is disabled. 8.3.2.4 additive latency (al) additive latency (al) operation is supported to make command and data bus efficient for sustainable bandwidths in ddr3l sdram. in this operation, t he ddr3l sdram allows a read or write command (either with or without auto - precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency ( rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the sum of the al and cas write latency (cwl) register settings. a summary of the al register options are shown in t able 2 . table 2 C additiv e latency (al) settings a4 a3 al 0 0 0 (al disabled) 0 1 cl - 1 1 0 cl - 2 1 1 reserved note: al has a value of cl - 1 or cl - 2 as per the cl values programmed in the mr0 register . 8.3.2.5 write levelin g for better signal integrity, ddr3l memory module adopted fly - by topology for the commands, addresses, control signals, and clocks. the fly - by topology has the benefit of reducing the number of stubs and their length, but it also causes flight time skew between clock and strobe at every dra m on the dimm. this makes it difficult for the c ontroller to maintain t dqss , t dss , and t dsh specification. therefore, the ddr3l sdram supports a write leveling feature to allow the controller to compensate for skew . see section 8 .9 write leveling on page 30 for more details.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 21 - 8.3.2.6 output disable the ddr3l sdram outputs may be enabled/disabled by mr1 (bit a12) as shown in figure 6 . w hen this feature is enabled (a12 = 1), all output pins (dqs, dqs, dqs#, etc.) are disconnected from the device, thus removing any loading of the output drivers. this feature may be useful when measuring module power, for example. for normal operation, a12 should be set to 0 . 8.3.2.7 tdqs, tdqs# tdqs (termination data strobe) provides additional termination resistance outputs that may be useful in some system configurations. when enabled via the mode register, the same termination resistance function is applied to the tdqs/tdqs# pins that is applied to the dqs/dqs# pins. in contrast to the rdqs function of ddr2 sdram, tdqs provides the termination resistance function only. the data strobe function of rdqs is not provided by tdqs. the tdqs and dm functions share the same pin. when the tdqs function is enabled via the mode register, the dm function is not supported. when the tdqs function is disabled, the dm function is provided and the tdqs# pin is not used. see table 3 for details. table 3 C tdqs, tdqs# function mat rix mr1 (a11) dm / tdqs nu / tdqs # 0 (tdqs disabled) dm hi - z 1 (tdqs enabled) tdqs tdqs# note s : 1. if tdqs is enabled, the dm function is disabled . 2. when not used, tdqs function can be disabled to save termination power .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 22 - 8.3.3 mode register mr 2 the mode register mr2 stores the data for controlling refresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and low on ba0 and ba2, while controlling the states of add ress pins according to the figure 7 below . note s : 1. ba2, a8, a11 ~ a1 4 are reserved for future use and must be programmed to 0 during mrs . 2. the rtt_wr value can be applied during writes even when rtt_nom is disabled. during write leveling, dynamic odt is not available . figure 7 C mr 2 definition b a 0 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 r t t _ w r a s r a d d r e s s f i e l d m o d e r e g i s t e r 2 b a 1 b a 0 0 0 0 0 1 1 1 1 m r 0 m r 1 m r 2 m r 3 5 ( t c k ( a v g ) 2 . 5 n s ) 8 ( 1 . 5 n s > t c k ( a v g ) 1 . 2 5 n s ) 9 ( 1 . 2 5 n s > t c k ( a v g ) 1 . 0 7 n s ) 6 ( 2 . 5 n s > t c k ( a v g ) 1 . 8 7 5 n s ) 7 ( 1 . 8 7 5 n s > t c k ( a v g ) 1 . 5 n s ) a 5 a 4 a 3 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 a 7 1 0 n o r m a l o p e r a t i n g t e m p e r a t u r e r a n g e e x t e n d e d o p e r a t i n g t e m p e r a t u r e r a n g e 1 0 a s r e n a b l e m a n u a l s r r e f e r e n c e ( s r t ) a 1 4 a 1 3 0 0 * 1 r e s e r v e d r e s e r v e d r e s e r v e d 1 1 1 1 0 0 1 1 1 a 1 0 0 0 1 1 a 9 0 1 0 1 d y n a m i c o d t o f f ( w r i t e d o e s n o t a f f e c t r t t v a l u e ) r e s e r v e d r z q / 4 r z q / 2 0 * 1 s r t c w l p a s r b a 1 1 b a 2 0 * 1 a 6 m r s e l e c t a u t o s e l f r e f r e s h ( a s r ) s e l f r e f r e s h t e m p e r a t u r e ( s r t ) r a n g e r t t _ w r * 2 c a s w r i t e l a t e n c y ( c w l ) a 2 0 0 0 0 1 1 1 1 a 1 0 0 1 1 0 0 1 1 a 0 0 1 0 1 0 1 1 0 f u l l a r r a y 1 / 8 t h a r r a y ( b a [ 2 : 0 ] = 0 0 0 ) 3 / 4 a r r a y ( b a [ 2 : 0 ] = 0 1 0 , 0 1 1 , 1 0 0 , 1 0 1 , 1 1 0 & 1 1 1 ) 1 / 8 t h a r r a y ( b a [ 2 : 0 ] = 1 1 1 ) q u a r t e r a r r a y ( b a [ 2 : 0 ] = 1 1 0 & 1 1 1 ) h a l f a r r a y ( b a [ 2 : 0 ] = 0 0 0 , 0 0 1 , 0 1 0 & 0 1 1 ) q u a r t e r a r r a y ( b a [ 2 : 0 ] = 0 0 0 & 0 0 1 ) h a l f a r r a y ( b a [ 2 : 0 ] = 1 0 0 , 1 0 1 , 1 1 0 & 1 1 1 ) p a r t i a l a r r a y s e l f r e f r e s h f o r 8 b a n k s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 23 - 8.3.3.1 partial array self refresh (pasr) if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified address range shown in figure 7 will be lost if self refresh is entered. data integrity will be maintained if t refi conditions are met and no self refresh command is issued . 8.3.3.2 cas write latency (cwl) the cas write latency is defined by mr2 (bits a3 - a5), as shown in figure 7 . cas write latency is the delay, in clock cycles, between the internal write command and the availability of the first bit of input data. ddr3l sdram does not support any half - clock latencies. the overall write latency (wl) is defined as additive latency (al) + cas w rite latency (cwl); wl = al + cwl. for more information on the supported cwl and al settings based on the operating clock frequency , refer to section 10 .1 5 speed bins on page 1 3 3 . for detailed write operation refer to section 8 .14 write operation on page 5 6 . 8.3.3.3 auto self refresh (asr) and self refresh temperature (srt) ddr3l sdram must support self refresh operation at all supported temperatures. applications requiring self refresh oper ation in the extended temperature range must use the asr function or program the srt bit appropriately. when asr enabled, ddr3l sdram automatically provides self refresh power management functions for all supported operating temperature values. if not enab led, the srt bit must be programmed to indicate t oper during subsequent self refresh operation. asr = 0, self refresh rate is determined by srt bit a7 in mr2 . asr = 1, self refresh rate is determined by on - die thermal sensor. srt bit a7 in mr2 is don't car e . 8.3.3.4 dynamic odt (rtt_wr) ddr3l sdram introduces a new feature dynamic odt . in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3l sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 configure the dynamic odt set t ings. in write leveling mode, only r tt _nom is available . for details on dynamic odt operation, refer to section 8 . 19 . 3 dynamic odt on page 8 3 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 24 - 8.3.4 mode register mr 3 the mode register mr3 controls multi purpose registers. the mode register 3 is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and ba0, and low on ba2 while controlling the states of address pins according to the figure 8 below . note s : 1. ba2, a3 ~ a1 4 are reserved for future use and must be programmed to 0 during mrs . 2. the predefined pattern will be used for read synchronizatio n . 3. when mpr control is set for normal operation (mr3 a[2] = 0) then mr3 a[1:0] will be ignored . figure 8 C mr3 definitio n 8.3.4.1 multi purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and t rp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). power down mode, self refresh, and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode . for detailed mpr operation refer to section 8 .10 multi purpose register on page 3 4 . b a 0 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a d d r e s s f i e l d m o d e r e g i s t e r 3 b a 0 0 0 0 0 1 1 1 1 m r 0 m r 1 m r 2 m r 3 1 0 d a t a f l o w f r o m m p r n o r m a l o p e r a t i o n * 3 a 1 4 a 1 3 1 m p r l o c m p r 0 * 1 m p r o p e r a t i o n a 1 0 0 0 0 1 1 1 1 p r e d e f i n e d p a t t e r n * 2 r f u r f u r f u m p r a d d r e s s b a 1 1 b a 2 0 * 1 b a 1 a 2 m p r m p r l o c a t i o n a 0 m r s e l e c t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 25 - 8.4 no operation (nop) command the no operation (nop) command is used to instruct the selected ddr3l sdram to perform a nop (cs# low and ras#, cas#, and we# high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected . 8.5 deselect command the deselect function (cs# high) prevents new commands from being executed by the ddr3l sdram. the ddr3l sdram is effectiv ely deselected. operations already in progress are not affected . 8.6 dll - off mode ddr3l dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operations until a0 bit is set back to 0. the mr1 a0 bit for dll control ca n be switched either during initialization or later. refer to section 8 . 8 input clock frequency change on page 2 8 . the dll - off mode operations listed below are an optional feature for ddr3l . the maximum clock frequency for dll - off mode is specified by the parameter t ck ( dll_off ) . there is no m inimum frequency limit besides the need to satisfy the refresh interval, t refi . due to latency counter and timing restrictions, only one value of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll - off mode is only required to support setting of both cl=6 and cwl=6. dll - off mode will affect the read data clock to data strobe relationship (t dqsck ), but not the data strobe to data relationship (t dqsq , t qh ). special attention is needed to line up read data to controller time domai n. comparing with dll - on mode, where t dqsck starts from the rising clock edge (al+cl) cycles after the read command, the dll - off mode t dqsck starts (al+cl - 1) cycles after the read command. another difference is that t dqsck may not be small compared to t ck (it might even be larger than t ck ) and the difference between t dqsck min and t dqsck max is significantly larger than in dll - on mode. the timing relations on dll - off mode read operation is shown in the following timing diagram (cl=6, bl=8): figure 9 C dll - off mode read timing operatio n t r a n s i t i o n i n g d a t a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d r e a d a d d r e s s n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p b a n k c o l b d o n ' t c a r e d q s , d q s # ( d l l _ o n ) d q ( d l l _ o n ) d q s , d q s # ( d l l _ o f f ) d q ( d l l _ o f f ) d q s , d q s # ( d l l _ o f f ) d q ( d l l _ o f f ) r l ( d l l _ o n ) = a l + c l = 6 ( c l = 6 , a l = 0 ) c l = 6 r l ( d l l _ o f f ) = a l + ( c l C 1 ) = 5 t d q s c k ( d l l _ o f f ) _ m i n t d q s c k ( d l l _ o n ) _ m a x d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 n o t e : t h e t d q s c k i s u s e d h e r e f o r d q s , d q s # a n d d q t o h a v e a s i m p l i f i e d ; t h e d l l _ o f f s h i f t w i l l a f f e c t b o t h t i m i n g s i n t h e s a m e w a y a n d t h e s k e w b e t w e e n a l l d q , a n d d q s , d q s # s i g n a l s w i l l s t i l l b e t d q s q .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 26 - 8.7 dll on/off switching procedure ddr3l dll - off mode is entered by setting mr1 bit a0 to 1; this will disable the dll for subsequent operations until a0 bit is set back to 0. 8.7.1 dll on to dll off procedure to switch from dll on to dll off requires the frequency to be changed during self - refresh, as outlined in the following procedure: 1. starting from idle state (all banks pre - charged, all timings fulfilled, and drams on - die termination res istors, r tt , must be in high impedance state before mrs to mr1 to disable the dll.) 2. set mr1 bit a0 to 1 to disable the dll . 3. wait t mod . 4. enter self refresh mode; wait until (t cksre ) is satisfied. 5. change frequency, in guidance with section 8 . 8 input clock frequency change on page 2 8 . 6. wait until a stable clock is available for at least (t cksrx ) at dram inputs. 7. starting with the self refresh exit command , cke must continuously be registered high until all t mod timings from any mrs command are satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until all t mod timings from any mrs command are satisfied. if both odt features were disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high . 8. wait t xs , then set mode registers with appropriate values (especially an update of cl, cwl and wr may be necessary. a zqcl command may also be issued after t xs ) . 9. wait for t mod , then dram is ready for next command. figure 1 0 C dll switch sequence from dll - on to dll - off t i m e b r e a k d o n ' t c a r e t 0 t 1 t a 0 t a 1 t b 0 t c 0 t d 0 t d 1 t e 0 t e 1 t f 0 c k # c k c k e c o m m a n d s r e * 3 n o p s r x * 6 n o p m r s * 7 n o p v a l i d * 8 o d t m r s * 2 n o p v a l i d * 8 * 1 t m o d t c k s r e * 4 t x s t m o d t c k e s r v a l i d 8 o d t : s t a t i c l o w i n c a s e r t t _ n o m a n d r t t _ w r i s e n a b l e d , o t h e r w i s e s t a t i c l o w o r h i g h n o t e s : 1 . s t a r t i n g w i t h i d l e s t a t e , r t t i n h i - z s t a t e 2 . d i s a b l e d l l b y s e t t i n g m r 1 b i t a 0 t o 1 3 . e n t e r s r 4 . c h a n g e f r e q u e n c y 5 . c l o c k m u s t b e s t a b l e t c k s r x 6 . e x i t s r 7 . u p d a t e m o d e r e g i s t e r w i t h d l l o f f p a r a m e t e r s s e t t i n g 8 . a n y v a l i d c o m m a n d t c k s r x * 5
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 27 - 8.7.2 dll off to dll on procedure to switch from dll off to dll on (with required frequency change) during self - refresh : 1. starting from idle state (all banks pre - charged, all timings fulfilled and drams on - die termination resistors (r tt ) must be in high impedance stat e before self - refresh mode is entered.) 2. enter self refresh mode, wait until t cksre satisfied. 3. change frequency, in guidance with section 8 . 8 input clock frequency change on page 2 8 . 4. wait until a stable clock is available for at least (t cksrx ) at dram inputs. 5. starting with the self refresh exit command, cke must continuously be registered high until t dllk tim ing from subsequent dll reset command is satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until t dllk timings from subsequent dll reset com mand is satisfied. if both odt features are disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high . 6. wait t xs , then set mr1 bit a0 to 0 to enable the dll. 7. wait t mrd , then set mr0 bit a8 to 1 to start dll reset . 8. wait t mrd , then set mode registers with appropriate values (especially an update of cl, cwl and wr may be necessary. after t mod satisfied from any proceeding mrs command, a zqcl command may also be issued during or after t dllk .) 9. wait for t mod , then dram is ready for next command (remember to wait t dllk after dll reset before applying command requiring a locked dll!). in addition, wait also for t zq oper in case a zqcl command was issued. figure 1 1 C dll switch sequence from dll off to dll on t i m e b r e a k d o n ' t c a r e t 0 t a 0 t a 1 t b 0 t c 0 t d 0 t e 0 t f 1 t g 0 t h 0 c k # c k c k e c o m m a n d n o p s r x * 5 m r s * 6 m r s * 7 m r s * 8 v a l i d * 9 o d t n o p s r e * 2 v a l i d * 1 t c k s r e t c k s r x * 4 t m r d t m r d t c k e s r o d t : s t a t i c l o w i n c a s e r t t _ n o m a n d r t t _ w r i s e n a b l e d , o t h e r w i s e s t a t i c l o w o r h i g h n o t e s : 1 . s t a r t i n g w i t h i d l e s t a t e 2 . e n t e r s r 3 . c h a n g e f r e q u e n c y 4 . c l o c k m u s t b e s t a b l e t c k s r x 5 . e x i t s r 6 . s e t d l l o n b y m r 1 a 0 = 0 7 . u p d a t e m o d e r e g i s t e r s 8 . a n y v a l i d c o m m a n d t c 1 t d l l k t x s * 3 o d t l o f f + 1 x t c k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 28 - 8.8 input clock frequency change once the ddr3l sdram is initialized, the ddr3l sdram requires the clock to be stable during almost all states of normal operation. this means that, once the clock frequency has been set and is to be in the stable state, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specifications . the input clock frequency can be changed from one stable clock rate to another st able clock rate under two conditions: (1) self - refresh mode and (2) precharge power - down mode. outside of these two modes, it is illegal to change the clock frequency. 8.8.1 frequency change during self - refresh for the first condition, once the ddr3l sdram has b een successfully placed in to self - refresh mode and t cksre has been satisfied, the state of the clock becomes a d on't care . once a d on't care , changing the clock frequency is permissible, provided the new clock frequency is stable prior to t cksrx. when entering and exiting self - refresh mode for the sole purpose of changing the clock frequency, the self - refresh entry and exit specifications must still be met as outlined in s ee section 8 .16 self - refresh operation on page 6 7 . the ddr3l sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. any frequency cha nge below the minimum operating frequency would require the use of dll_on mode - > dll_off mode transition sequence; refer to section 8 .7 dll on/off switching procedure on page 2 6 . 8.8.2 frequency change during precharge power - down the second condition is when the ddr3l sdram is in precharge power - down mode (either fast exit mode or slow exit mode). if the r tt _n om feature was enabled in the mode register prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring r tt is in an off state. if the r tt _n om feature was disabled in the mode register prior to entering precharge power down mode, r tt will remain in the off state. the odt signal can be registered either low or high in this case. a minimum of t cksre must occur after cke goes low before the clock frequency may change. the ddr3l sdram input clock frequency is allowed t o change only within the minimum and maximum operating frequency specified for the particular speed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, stable new clocks must be provided to the dram t cksrx before precharge power - down may be exited; after precharge power - down is exited and t xp has expired, the dll must be reset via mrs. depending on the new clock frequency, additional mrs commands may need to be issued to a ppropriately set the wr, cl, and cwl with cke continuously registered high. during dll re - lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequency. this process is depicted in figure 1 2 on page 2 9 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 29 - note s : 1. applicable for both slow exit and fast exit precharge power - down . 2. t aofpd and t aof must be satisfied and outputs high - z prior to t1; refer to odt timing section for exact requirements . 3. if the r tt _ n om feature was enabled in the mode register prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring r tt is in an off state, as shown in figure 9 . if the r tt _n om feature was disabled in the mode register prior to entering precharge power down mode, r tt will remain in the off state. the odt signal can be registered either low or high in this case . figure 1 2 C c hange frequency during precharge power - down t i m e b r e a k d o n ' t c a r e t 0 t 1 t 2 t a 0 t b 0 t c 1 t d 0 t d 1 t e 0 t e 1 c k # c k c k e c o m m a n d n o p n o p n o p m r s n o p v a l i d o d t n o p n o p t c 0 d l l r e s e t v a l i d a d d r e s s d q s , d q s # d q d m t c h t c l t c k t i h t i s t c k s r e t c k e t c p d e d t i h t i s t c k b t c h b t c l b t c k b t c h b t c l b t c k b t c h b t c l b t x p t i h t i s h i g h - z h i g h - z t a o f p d / t a o f t d l l k e x i t p r e c h a r g e p o w e r - d o w n m o d e f r e q u e n c y c h a n g e e n t e r p r e c h a r g e p o w e r - d o w n m o d e p r e v i o u s c l o c k f r e q u e n c y n e w c l o c k f r e q u e n c y t c k s r x
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 30 - 8.9 write leveling for better signal integrity, the ddr3l memory module adopted fly - by topology for the commands, addresses, control signals, and clocks. the fly - by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every dra m on the dimm. this makes it difficult for the controller to maintain t dqss , t dss , and t dsh specification. therefore, the ddr3l sdram supports a write leveling feature to allow the controller to compensate for skew. the memory controller can use the wri te leveling feature and feedback from the ddr3l sdram to adjust the dqs - dqs# to ck - ck# relationship. the memory controller involved in the leveling must have adjustable delay setting on dqs - dqs# to align the rising edge of dqs - dqs# with that of th e clock at the dram pin. the dram asynchronously feeds back ck - ck#, sampled with the rising edge of dqs - dqs#, through the dq bus. the controller repeatedly delays dqs - dqs# until a transition from 0 to 1 is detected. the dqs - dqs# delay established t hough this exercise would ensure t dqss specification. besides t dqss , t dss and t dsh specification also needs to be fulfilled. one way to achieve this is to combine the actual t dqss in the application with an appropriate duty cycle and jitter on the dqs - dqs# signals. depending on the actual t dqss in the application, the actual values for t dqsl and t dqsh may have to be better than the absolute limits provided in section 10 .16 ac characteristics in order to satisfy t dss and tdsh specification. a conceptual timing of this scheme is shown in figure 1 3 . figure 1 3 C write leveling concept dqs - dqs# driven by the controller during leveling mode must be terminated by the dram based on ranks populated. similarly, the dq bus driven by the dram must also be terminated at the controller. c k # c k t 0 t 1 t 2 t 3 t 4 t 6 t 7 t 5 t 0 t 1 t 2 t 3 t 4 t 6 t 5 t n c k # c k d i f f _ d q s d i f f _ d q s d i f f _ d q s d q d q 0 o r 1 0 0 0 0 o r 1 1 1 1 s o u r c e d e s t i n a t i o n p u s h d q s t o c a p t u r e 0 - 1 t r a n s i t i o n
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 31 - 8.9.1 dram setting for write leveling & dram termination function in that mode dram enters into write leveling mode if a7 in mr1 set high and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set low (table 4 ). note that in write leveling mode, only dqs/dqs# terminations are activated and deactivated via odt pin, unlike normal operation (table 5 ) . table 4 C mr setting involved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 table 5 C dram termination function in the leveling mode odt pin @dram dqs/dqs# termination dq s termination de - asserted off off a sserted on off n ote: in write leveling mode with its output buffer disabled (mr1 a [7] = 1 with mr1 a [12] = 1) all r tt _nom settings are allowed; in write leveling mode with its output buffer enabled (mr1 a [7] = 1 with mr1 a [ 12] = 0) only r tt _nom settings of rzq/2, rzq/4 and rzq/6 are allowed . 8.9.2 write leveling procedure the memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. when entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only nop or deselect commands are allowed , as well as an mrs command to change qoff bit (mr1[a12]) and an mrs command to exit write leveling (mr1[a7]). upon exiting write leveling mode, the mrs command performing the exit (mr1[a7]=0) may also change mr1 bits of a12, a9, a6 - a5, and a2 - a1 . since the controller levels one rank at a time, th e output of other ranks must be disabled by setting mr1 bit a12 to 1. the controller may assert odt after t mod , at which time the dram is ready to accept the odt signal. the controller may drive dqs low and dqs# high after a delay of t wldqsen , at which time the dram has applied on - die termination on these signals. after t dqsl and t wlmrd , the controller provides a single dqs, dqs# edge which is used by the dram to sample ck - ck# driven from controller. t wlmrd (max) timing is controller dependent. dram sam ples ck - ck# status with rising edge of dqs - dqs# and provides feedback on all the dq bits asynchronously after t wlo timing. either one or all data bits ("prime dq bit(s)") provide the leveling feedback. the dram's remaining dq bits are driven low static ally after the first sampling procedure. there is a dq output uncertainty of t wloe defined to allow mismatch on dq bits. the t wloe period is defined from the transition of the earliest dq bit to the corresponding transition of the latest dq bit. there are no read strobes (dqs/dqs#) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs - dqs# delay setting and launches the next dqs/dqs# pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs - dqs# delay setting and write leveling is achieved for the device. figure 1 4 describes the timing diagram and parameters for the overall write leveling procedure .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 32 - note s : 1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remaining dqs must be driven low, as shown in above figure, and maintained at this state through out the leveling procedure . 2. mrs: load mr1 to enter write leveling mode . 3. nop: nop or deselect . 4. diff_dqs is the differential data strobe (dqs, dqs#). timing reference points are the ze ro crossings. dqs is shown with solid line, dqs# is shown with dotted line . 5. ck, ck# : ck is shown with solid dark line, where as ck# is drawn with dotted line. 6. dqs, dqs# needs to fulfill minimum pulse width requirements t dqsh (min) and t dqsl (min) as defined for regular writes; the max pulse width is system dependent. figure 1 4 C timing details of write leveling sequence [dqs - dqs# is capturing ck - ck# low at t1 and ck - ck# high at t2 ] t i m e b r e a k d o n ' t c a r e c k # * 5 o d t c o m m a n d d i f f _ d q s * 4 p r i m e d q * 1 o n e p r i m e d q : l a t e r e m a i n i n g d q s e a r l y r e m a i n i n g d q s l a t e p r i m e d q s * 1 e a r l y p r i m e d q s * 1 a l l d q s a r e p r i m e : m r s * 2 n o p * 3 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t m o d t w l d q s e n t w l m r d t w l m r d t d q s l * 6 t d q s h * 6 t d q s l * 6 t d q s h * 6 t w l o t w l o t w l o e t w l o t w l o t w l o e t w l o t w l o e t w l o t w l o t w l o t 1 t w l s t w l h t 2 t w l s t w l h u n d e f i n e d d r i v i n g m o d e c k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 33 - 8.9.3 write leveling mode exit the following sequence describes how the write leveling mode should be exited: 1. after the last rising strobe edge (see ~t0), stop driving the strobe signals (see ~tc0). note: f rom now on, dq pins are in undefined driving mode, and will remain undefined, until t mod after the respective mr command (te1) . 2. drive odt pin low (t is must be satisfied) and continue registering low. (see tb0) . 3. after the r tt is switched off, disable write level mode via mrs command (see tc2) . 4. after t mod is satisfied (te1), any valid command may be registered. (mr commands may be issued after t mrd (td1) . note: 1. the dq result = 1 between ta0 and tc0 is a result of the dqs, dqs# signals capturing ck high just after the t0 state . figure 1 5 C timing details of write leveling exit t i m e b r e a k d o n ' t c a r e c k # c k c o m m a n d n o p n o p n o p n o p n o p n o p n o p m r s n o p v a l i d n o p v a l i d t 0 t 1 t 2 t a 0 t b 0 t c 0 t c 1 t c 2 t d 0 t d 1 t e 0 t e 1 m r 1 v a l i d v a l i d t w l o r e s u l t = 1 t a o f m a x t a o f m i n t i s t m o d t r a n s i t i o n i n g a d d r e s s o d t r t t _ d q s _ d q s # d q s _ d q s # r t t _ d q d q * 1 t m r d o d t l o f f r t t _ n o m u n d e f i n e d d r i v i n g m o d e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 34 - 8.10 multi purpose register the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. the basic concept of the mpr is shown in figure 1 6 . figure 1 6 C mpr block diagram to enable the mpr, a m ode register set (mrs) command must be issued to mr3 register with bit a2 = 1, as shown in table 5 . prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and t rp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. the resulting operation, when a rd or rda command is issued, is defined by mr3 bits a[1:0] when the mpr is enabled as shown in table 7 . when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). note that in mpr mode rda has the same functionality as a read command which means the auto precharge part of rda is ignored. power - down mode, self - refresh, and any other non - rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mod e. table 6 C mpr functional description of mr3 bits mr3 a[2] mr3 a[1:0] function mpr mpr - loc 0b don't care (0b or 1b) normal operation, no mpr transaction all subsequent reads will come from dram array all subsequent write will go to dram array 1b see table 7 enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0] m u l t i p u r p o s e r e g i s t e r p r e - d e f i n e d d a t a f o r r e a d s m r 3 [ a 2 ] d q , d m , d q s , d q s # m e m o r y c o r e ( a l l b a n k s p r e c h a r g e d )
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 3 5 - 8.10.1 mpr functional description ? one bit wide logical interface via all dq pins during read operation . ? register read : dq[0] drive information from mpr dq[7:1] either d rive the same information as dq [0] , or they drive 0b ? addressing during for multi purpose register reads for all mpr agents: ba[2:0]: d on't care a[1:0]: a[1:0] must be equal to 00b. data read burst order in nibble is fixed a[2] : a[2] selects the burst order for bl=8, a[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) for burst chop 4 cases, the burst order is switched on nibble base a[2]=0b, burst order: 0,1,2,3 * ) a[2]=1b, burst order: 4,5,6,7 * ) a[9:3]: d on't care a10/ap: d on't care a12/bc #: selects burst chop mode on - the - fly, if enabled within mr0 a11 , a13 and a14 : d on't care ? regular interface functionality during register reads: support two burst ordering which are switched with a2 and a[1:0]=00b support of read burst chop (mrs and on - the - fly via a12/bc # ) all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3l sdram regular read latencies and ac timings apply dll mu st be locked prior to mpr reads n ote: *) burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 36 - 8.10.2 mpr register address definition table 7 provides an overview of the available data locations, how they are addressed by mr3 a[1:0] during a mrs to mr3, and how their individual bits are mapped into the burst order bits during a multi purpose register read . table 7 C mpr readout s and burst order bit mapping mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read pre - defined pattern for system calibration bl8 000b burst order 0,1,2,3,4,5,6,7 pre - defined data pattern [0,1,0,1,0,1,0,1] bc4 000b burst order 0,1,2,3 pre - defined data pattern [0,1,0,1] bc4 100b burst order 4,5,6,7 pre - defined data pattern [0,1,0,1] 1b 01b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 b c4 000b burst order 0,1,2,3 b c4 100b burst order 4,5,6,7 1b 10b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 b c4 000b burst order 0,1,2,3 b c4 100b burst order 4,5,6,7 1b 11b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 b c4 000b burst order 0,1,2,3 b c4 100b burst order 4,5,6,7 n ote: burst order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent . 8.10.3 relevant timing parameters the following ac timing parameters are important for operating the multi purpose register: t rp , t mrd , t mod , and t mprr . for more details refer to section 10 .1 6 ac characteristics on page 1 3 7 . 8.10.4 protocol example protocol example (this is one example): read out pre - determined read - calibration pattern. description: multiple reads from multi purpose register, in order to do system level read timing calibration based on pre - determined and standardized pattern. protocol steps: ? precharge all. ? wait until t rp is satisfied . ? set mrs , mr3 a [ 2 ] = 1b and mr3 a [1:0] = 00b . this r edirect s all subsequent reads and load p re - defined pattern into multi purpose register . ? wait until t mrd and t mod are satisfied (multi purpose register is then ready to be read). during the period mr3 a[ 2 ] =1, no data write operation is allowed.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 37 - ? read: a[1:0] = 00b (data burst order is fixed s tarting at nibble, always 00b here) a[2] = 0b (for bl=8, burst order is fixed as 0,1,2,3,4,5,6,7) a12/bc # = 1 (use regular burst length of 8) all other address pins (including ba[2:0] and a10/ap): don't care ? after rl = al + cl, dram bursts out the pre - de fined read calibration pattern. ? memory controller repeats these calibration reads until read data capture at memory controller is optimized. ? after end of last mpr read burst, wait until t mprr is satisfied. ? set mrs , mr3 a[ 2 ] = 0 b and mr3 a [1:0] = don't care to the normal dram state. all subsequent read and write accesses will be regular reads and writes from/to the dram array . ? wait until t mrd and t mod are satisfied . ? continue with regular dram commands, like activate a memory bank for regular read or write access,...
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 38 - figure 17 C mpr readout of pre - defined pattern, bl8 fixed burst order, single readout c k # c k c o m m a n d p r e a m r s r e a d * 1 n o p n o p n o p n o p n o p n o p n o p n o p m r s t 0 t a t b 0 t b 1 t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 b a n o p n o p v a l i d 3 3 0 0 * 2 v a l i d 1 0 * 2 0 0 0 0 0 0 0 0 0 0 0 1 a [ 1 : 0 ] a [ 2 ] a [ 9 : 3 ] a 1 0 / a p a [ 1 1 ] a 1 2 / b c # d q s , d q s # d q r l t r p t m o d v a l i d * 1 v a l i d v a l i d v a l i d v a l i d t m p r r t m o d t c 8 t c 9 t d n o t e s : 1 . r d w i t h b l 8 e i t h e r b y m r s o r o n t h e f l y . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 2 : 0 ] . t i m e b r e a k d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 39 - figure 18 C mpr readout of pre - defined pattern, bl8 fixed burst order, back - to - back readout c k # c k c o m m a n d p r e a m r s r e a d * 1 n o p n o p n o p n o p n o p n o p n o p n o p t 0 t a t b 0 t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 b a n o p m r s v a l i d 3 0 0 * 2 1 0 * 2 0 0 0 0 0 1 a [ 1 : 0 ] a [ 2 ] a [ 9 : 3 ] a 1 0 / a p a [ 1 1 ] a 1 2 / b c # d q s , d q s # d q r l v a l i d * 1 v a l i d v a l i d v a l i d v a l i d t m p r r t c 8 t c 9 t d t 1 0 3 v a l i d v a l i d 0 0 0 v a l i d 0 v a l i d 0 v a l i d 0 v a l i d * 1 r l 0 * 2 0 * 2 r e a d * 1 t i m e b r e a k d o n ' t c a r e n o t e s : 1 . r d w i t h b l 8 e i t h e r b y m r s o r o n t h e f l y . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 2 : 0 ] . t m o d t c c d t m o d t r p
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 40 - figure 19 C mpr readout pre - defined pattern, bc4, lower nibble then upper nibble t i m e b r e a k d o n ' t c a r e c k # c k c o m m a n d p r e a m r s r e a d * 1 n o p n o p n o p n o p n o p n o p n o p m r s t 0 t a t b 0 t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 b a n o p n o p v a l i d 3 0 0 * 2 1 0 * 3 0 0 0 0 0 1 a [ 1 : 0 ] a [ 2 ] a [ 9 : 3 ] a 1 0 / a p a [ 1 1 ] a 1 2 / b c # d q s , d q s # d q r l v a l i d * 1 v a l i d v a l i d v a l i d v a l i d t m p r r t m o d t c 8 t c 9 t d t 1 0 v a l i d v a l i d v a l i d v a l i d v a l i d * 1 r l 0 * 2 1 * 4 r e a d * 1 3 v a l i d 0 0 0 0 0 0 n o t e s : 1 . r d w i t h b c 4 e i t h e r b y m r s o r o n t h e f l y . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 1 : 0 ] . 3 . a [ 2 ] = 0 s e l e c t s l o w e r 4 n i b b l e b i t s 0 . . . . 3 . 4 . a [ 2 ] = 1 s e l e c t s u p p e r 4 n i b b l e b i t s 4 . . . . 7 . t c c d t m o d t r p
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 41 - figure 20 C mpr readout of pre - defined pattern, bc4, upper nibble then lower nibbl e t i m e b r e a k d o n ' t c a r e c k # c k c o m m a n d p r e a m r s r e a d * 1 n o p n o p n o p n o p n o p n o p n o p m r s t 0 t a t b 0 t c 0 t c 1 t c 2 t c 3 t c 4 t c 5 t c 6 t c 7 b a n o p n o p v a l i d 3 0 0 * 2 1 1 * 4 0 0 0 0 0 1 a [ 1 : 0 ] a [ 2 ] a [ 9 : 3 ] a 1 0 / a p a [ 1 1 ] a 1 2 / b c # d q s , d q s # d q r l v a l i d * 1 v a l i d v a l i d v a l i d v a l i d t m p r r t m o d t c 8 t c 9 t d t 1 0 v a l i d v a l i d v a l i d v a l i d v a l i d * 1 r l 0 * 2 0 * 3 r e a d * 1 3 v a l i d 0 0 0 0 0 0 n o t e s : 1 . r d w i t h b c 4 e i t h e r b y m r s o r o n t h e f l y . 2 . m e m o r y c o n t r o l l e r m u s t d r i v e 0 o n a [ 1 : 0 ] . 3 . a [ 2 ] = 0 s e l e c t s l o w e r 4 n i b b l e b i t s 0 . . . . 3 . 4 . a [ 2 ] = 1 s e l e c t s u p p e r 4 n i b b l e b i t s 4 . . . . 7 . t c c d t m o d t r p
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 42 - 8.11 active command the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0 - ba2 inputs selects the bank, and the address provided on inputs a0 - a1 4 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank . 8.12 precharge command the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time (t rp ) after the precharge command is issued, except in the case of concurrent auto precharge, where a read or write command to a d ifferent bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write comm ands being issued to that bank. a precharge command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. however, the precharge period will be determined by the last precharge command issued to the bank .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 43 - 8.13 read operation 8.13.1 read burst operation during a read or write command, ddr3l will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). a12 = 0, bc4 (bc4 = burst ch op, t ccd = 4) a12 = 1, bl8 a12 is used only for burst length control, not as a column address . note s : 1. bl8, rl = 6 , al = 0, cl = 6 . 2. d out n = data - out from column n . 3. nop commands are shown for ease of illustration; other commands may be valid at these times . 4. bl8 setting activated by either mr0 a [1:0 ] = 00 or mr0 a [1:0 ] = 01 and a12 = 1 during read command at t0. figure 21 C read burst operation rl = 6 (al = 0, cl = 6 , bl8) note s : 1. bl8, rl = 11 , al = (cl - 1), cl = 6 . 2. d out n = data - out from column n . 3. nop commands are shown for ease of illustration; other commands may be valid at these times . 4. bl8 setting activated by either mr0 a [1:0 ] = 00 or mr0 a [1:0 ] = 0 1 and a12 = 1 during read command at t0. figure 22 C read burst operation rl = 11 (al = 5 , cl = 6 , bl8) t r a n s i t i o n i n g d a t a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p n o p n o p n o p b a n k c o l n d o n ' t c a r e d q s , d q s # d q * 2 c l = 6 d o u t n d o u t n + 1 r l = a l + c l t r p r e d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t r p s t n o p n o p n o p t r a n s i t i o n i n g d a t a t 0 t 1 t 5 t 6 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 t 1 6 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p n o p n o p n o p b a n k c o l n d o n ' t c a r e d q s , d q s # d q * 2 c l = 6 d o u t n d o u t n + 1 r l = a l + c l t r p r e d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t r p s t n o p n o p n o p a l = 5 t i m e b r e a k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 44 - 8.13.2 read timing definitions read timing is shown in figure 2 3 and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? t dqsck min/max describes the allowed range for a rising data strobe edge relative to ck, ck#. ? t dqsck is the actual position of a rising strobe edge relative to ck, ck#. ? t qsh describes the dqs, dqs# differential output high time. ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh describes the earliest invalid trans ition of the associated dq pins . falling data strobe edge parameters : ? t qsl describes the dqs, dqs# differential output low time. ? t dqsq describes the latest valid transition of th e associated dq pins. ? t qh describes the earliest invalid transition of the associated dq pins. t dqsq ; both rising/falling edges of dqs, no t ac defined. figure 23 C r ead timing definition c k # c k d q s # d q s t q s h t q s l t d q s c k t d q s c k t d q s c k ( m i n ) t d q s c k ( m a x ) t d q s c k ( m i n ) t d q s c k ( m a x ) r i s i n g s t r o b e r e g i o n t q h t q h t d q s q a s s o c i a t e d d q p i n s t d q s q r i s i n g s t r o b e r e g i o n
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 45 - 8.13.2.1 read timing; clock to data strobe relationshi p clock to data strobe relationship is shown in figure 2 4 and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? t dqsck min/max describes the allowed range for a rising data strobe edge relative to ck, ck#. ? t dqsck is the actual position of a rising strobe edge relative to ck, ck#. ? t qsh describes the data strobe high pulse width. falling data strobe edge parameters : ? t qsl describes the data strobe low pulse width . t lz(dqs) , t hz(dqs) for preamble/postamble (see sectio n 8.13.2.3 and figure 26 ). note s : 1. within a burst, rising strobe edge is not necessarily fixed to be always at t dqsck (min) or t dqsck (max). instead, rising strobe edge can vary between t dqsck (min) and t dqsck (max). 2. not with standing note 1, a rising strobe edge with t dqsck (max) at t(n) can not be immediately followed by a rising strobe edge with t dqsck (min) at t(n+1). this is because other timing relationships (t qsh , t qsl ) ex ist: if t dqsck (n+1) < 0: t dqsck (n) < 1.0 t ck - (t qsh min + t qsl min) - | t dqsck (n+1) | 3. the dqs, dqs# differential output high time is defined by t qsh and the dqs, dqs# differential output low time is defined by t qsl . 4. likewise, t lz(dqs) min and t hz(dqs) min are not tied to t dqsck , min (early strobe case) and t lz(dqs) max and t hz(dqs) max are not tied to t dqsck , max (late strobe case). 5. the minimum pulse width of read preamble is defined by t rpre (min). 6. the maximum read postamble is bound by t dqsck (min) plus t qsh (min) on the left side and t hzdsq (max) on the right side. 7. the minimum pulse width of read postamble is defined by t rpst (min). 8. the maximum read preamble is bound by t lzdqs (min) on the left side and t dqsck (max) on the right side . figure 24 C clock to data strobe relationship c k / c k # t r p r e t l z ( d q s ) m i n t d q s c k ( m i n ) t d q s c k ( m i n ) t d q s c k ( m i n ) t d q s c k ( m i n ) t h z ( d q s ) m i n t q s h t q s l t q s h t q s l t q s h t q s l t q s h t q s l t q s h t q s l t q s h t q s l t r p s t t d q s c k ( m a x ) t d q s c k ( m a x ) t d q s c k ( m a x ) t d q s c k ( m a x ) b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 b i t 0 b i t 1 b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 t l z ( d q s ) m a x t h z ( d q s ) m a x d q s , d q s # e r l y s t r o b e d q s , d q s # l a t e s t r o b e t r p r e r l m e a s u r e d t o t h i s p o i n t t r p s t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 46 - 8.13.2.2 read timing; data strobe to data relationship the data strobe to data relationship is shown in figure 2 5 and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh describes the earliest invalid transition of the associated dq pins. falling data strobe edge parameters : ? t dqsq describes the latest valid transition of the associated dq pins. ? t qh descr ibes the earliest invalid transition of the associated dq pins. t dqsq ; both rising/falling edges of dqs, no t ac defined . note s : 1. bl = 8, rl = 6 (al = 0, cl = 6 ) . 2. d out n = data - out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 a [1:0 ] = 00 or mr0 a [1:0 ] = 0 1 and a12 = 1 during read command at t0. 5. output timings are referenced to v ddq /2, and dll on for locking. 6. t dqsq defines the skew b etween dqs, dqs# to data and do es not define dqs, dqs# to clock . 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary (either early or late) within a burst . figure 25 C d ata strobe to data relationship t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p n o p n o p n o p b a n k c o l n d q s , d q s # d q * 2 ( l a s t d a t a v a l i d ) d o u t n t r p r e t r p s t n o p n o p n o p r l = a l + c l d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 d o u t n + 1 d o u t n + 2 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t q h t d q s q ( m a x ) t d q s q ( m a x ) t q h d q * 2 ( f i r s t d a t a n o l o n g e r v a l i d ) a l l d q s c o l l e c t i v e l y t r a n s i t i o n i n g d a t a d o n ' t c a r e d o u t n d o u t n + 3 d o u t n + 3
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 47 - 8.13.2.3 t lz(dqs) , t lz(dq) , t hz(dqs) , t hz(dq) calculation t hz and t lz transitions occur in the same time window as valid data transitions. these parameters are referenced to a specific voltage level that specifies when the device output is no longer driving t hz(dqs) and t hz( dq) , or begins driving t lz(dqs) , t lz(dq) . figure 26 shows a method to calculate the point when the device is no longer driving t hz(dqs) and t hz(dq) , or begins driving t lz(dqs) , t lz(dq) , by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. the parameters t lz(dqs) , t lz(dq) , t hz(dqs) , and t hz(dq) are defined as singled ended. figure 26 C t lz and t hz method for calculating transitions and endpoints v t t + 2 x m v v t t + x m v v t t - x m v v t t - 2 x m v t 1 t 2 t l z c k c k # t l z ( d q s ) , t l z ( d q ) t l z ( d q s ) : c k C c k # r i s i n g c r o s s i n g a t r l - 1 t l z ( d q ) : c k C c k # r i s i n g c r o s s i n g a t r l t h z c k c k # t h z ( d q s ) , t h z ( d q ) w i t h b l 8 : c k C c k # r i s i n g c r o s s i n g a t r l + 4 n c k t h z ( d q s ) , t h z ( d q ) w i t h b c 4 : c k C c k # r i s i n g c r o s s i n g a t r l + 2 n c k v o h - x m v v o h - 2 x m v t 2 t 1 t h z ( d q s ) , t h z ( d q ) v o l + 2 x m v v o l + x m v t h z ( d q s ) , t h z ( d q ) e n d p o i n t = 2 * t 1 - t 2 t l z ( d q s ) , t l z ( d q ) b e g i n p o i n t = 2 * t 1 - t 2
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 48 - 8.13.2.4 t rpre calculation the method for calculating differential pulse widths for t rpre is shown in figure 27 . figure 2 7 C method for calculating t rpre transitions and endpoints 8.13.2.5 t rp st calculation the method for calculating differential pulse widths for t rp st is shown in figure 2 8 . figure 28 C method for calculating t rpst transitions and endpoints c k c k # s i n g l e e n d e d s i g n a l , p r o v i d e d a s b a c k g r o u n d i n f o r m a t i o n d q s d q s # s i n g l e e n d e d s i g n a l , p r o v i d e d a s b a c k g r o u n d i n f o r m a t i o n d q s - d q s # r e s u l t i n g d i f f e r e n t i a l s i g n a l , r e l e v a n t f o r t r p r e s p e c i f i c a t i o n t a t b t c t d t 2 t 1 t r p r e t r p r e _ e n d t r p r e _ b e g i n v t t 0 v t t v t t c k c k # s i n g l e e n d e d s i g n a l , p r o v i d e d a s b a c k g r o u n d i n f o r m a t i o n d q s d q s # s i n g l e e n d e d s i g n a l , p r o v i d e d a s b a c k g r o u n d i n f o r m a t i o n d q s - d q s # r e s u l t i n g d i f f e r e n t i a l s i g n a l , r e l e v a n t f o r t r p s t s p e c i f i c a t i o n v t t t a t b t d t c t 1 t r p s t t r p s t _ b e g i n t 2 t r p s t _ e n d v t t v t t 0
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 49 - figure 29 C read (bl8) to read (bl8) figure 3 0 C nonconsecutive read (bl8) to read (bl8), t ccd =5 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p r e a d n o p b a n k c o l n d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 r l = 6 t r p r e d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t r p s t n o p n o p n o p t 1 1 t 1 2 t 1 3 t 1 4 n o p b a n k c o l b n o p n o p n o p n o p d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 t c c d t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . b l 8 , r l = 6 ( c l = 6 , a l = 0 ) . 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 a [ 1 : 0 ] = 0 0 o r m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 4 . t 0 t 1 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p r e a d n o p b a n k c o l n d q s , d q s # * 5 d q * 2 r l = 6 r l = 6 t r p r e t r p s t n o p n o p n o p t 1 2 t 1 3 t 1 4 t 1 5 n o p b a n k c o l b n o p n o p n o p n o p t c c d = 5 t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . b l 8 , r l = 6 ( c l = 6 , a l = 0 ) , t c c d = 5 . 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 a [ 1 : 0 ] = 0 0 o r m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 5 . 5 . d q s - d q s # i s h e l d l o g i c l o w a t t 1 0 . d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 d o u t b + 7 t i m e b r e a k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 50 - figure 3 1 C read (b c4 ) to read (b c4 ) figure 3 2 C read (bl8) to write (bl8) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p r e a d n o p b a n k c o l n d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 r l = 6 t r p r e d o u t n + 2 d o u t n + 3 t r p s t n o p n o p n o p t 1 1 t 1 2 t 1 3 t 1 4 n o p b a n k c o l b n o p n o p n o p n o p t r p r e d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 t r p s t t c c d t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . b c 4 , r l = 6 ( c l = 6 , a l = 0 ) 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 a [ 1 : 0 ] = 1 0 o r m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d s a t t 0 a n d t 4 . t 0 t 1 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p n o p b a n k c o l n d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 w l = 5 t r p r e d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t w p s t n o p n o p w r i t e t 1 2 t 1 3 t 1 4 t 1 5 b a n k c o l b n o p n o p n o p n o p d i n b d i n b + 1 d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 d i n b + 6 d i n b + 7 t 1 6 n o p n o p n o p t r p s t t w p r e 4 c l o c k s t w r t w t r t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . b l 8 , r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 a [ 1 : 0 ] = 0 0 o r m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 a n d w r i t e c o m m a n d a t t 7 . r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l t i m e b r e a k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 51 - figure 3 3 C read (b c4 ) to write (b c4 ) otf figure 3 4 C read (bl8) to read (b c4 ) otf t 0 t 1 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p w r i t e n o p d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 w l = 5 t r p r e d o u t n + 2 d o u t n + 3 t w p s t n o p n o p n o p t 1 2 t 1 3 t 1 4 t 1 5 n o p n o p n o p n o p d i n b d i n b + 1 d i n b + 2 d i n b + 3 t 1 6 n o p n o p n o p t r p s t t w p r e 4 c l o c k s t w r t w t r t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . b c 4 , r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 0 a n d w r i t e c o m m a n d a t t 5 . b a n k c o l n b a n k c o l b r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l t i m e b r e a k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p r e a d n o p b a n k c o l n d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 r l = 6 t r p r e d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t r p s t n o p n o p n o p t 1 1 t 1 2 t 1 3 t 1 4 n o p b a n k c o l b n o p n o p n o p n o p d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 3 t c c d t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) . 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 4 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 52 - figure 3 5 C read (b c4 ) to read (b l8 ) otf figure 3 6 C read (b c4 ) to write (bl8) otf r l = 6 d o u t n d o u t n + 1 r l = 6 t r p r e d o u t n + 2 d o u t n + 3 t r p s t t r p r e d o u t b d o u t b + 1 d o u t b + 2 d o u t b + 7 t r p s t d o u t b + 3 d o u t b + 4 d o u t b + 5 d o u t b + 6 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p n o p r e a d n o p b a n k c o l n d q s , d q s # d q * 2 n o p n o p n o p t 1 1 t 1 2 t 1 3 t 1 4 n o p b a n k c o l b n o p n o p n o p n o p t c c d t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) 2 . d o u t n ( o r b ) = d a t a - o u t f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 0 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 4 . t 0 t 1 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p w r i t e n o p d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 w l = 5 t r p r e d o u t n + 2 d o u t n + 3 t w p s t n o p n o p n o p t 1 2 t 1 3 t 1 4 t 1 5 n o p n o p n o p n o p d i n b d i n b + 1 d i n b + 6 d i n b + 7 t 1 6 n o p n o p n o p t r p s t t w p r e 4 c l o c k s t w r t w t r t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g r e a d c o m m a n d a t t 0 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 5 . b a n k c o l n b a n k c o l b d i n b + 2 d i n b + 3 d i n b + 4 d i n b + 5 t i m e b r e a k r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d / 2 + 2 t c k - w l
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 53 - figure 3 7 C read (b l8 ) to write (b c4 ) otf t 0 t 1 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 c k # c k c o m m a n d * 3 r e a d a d d r e s s * 4 n o p n o p n o p r e a d n o p b a n k c o l n d q s , d q s # d q * 2 r l = 6 d o u t n d o u t n + 1 w l = 5 t r p r e d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t w p s t n o p n o p w r i t e t 1 2 t 1 3 t 1 4 t 1 5 b a n k c o l b n o p n o p n o p n o p d i n b d i n b + 1 d i n b + 2 d i n b + 7 t 1 6 n o p n o p n o p t r p s t t w p r e 4 c l o c k s t w r t w t r t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n , d i n b = d a t a - i n f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g r e a d c o m m a n d a t t 0 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 7 . r e a d t o w r i t e c o m m a n d d e l a y = r l + t c c d + 2 t c k - w l t i m e b r e a k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 54 - 8.13.2.6 burst read operation followed by a precharge the minimum external read command to precharge command spacing to the same bank is equal to al + t rtp with t rtp being the internal read command to precharge command delay. note that the minimum act to pre timing, t ras.min must be satisfied as well. the minimum value for the internal read command to precharge command delay is given by t rtp.min = max(4 n ck , 7.5 n s ). a new bank active command may be issued to the same bank if the following two conditions are satisfied simul taneously: 1. the minimum ras precharge time (t rp .min ) has been satisfied from the clock at which the precharge begins . 2. the minimum ras cycle time (t rc .min ) from the previous bank activation has been satisfied . examples of read commands followed by precharge are show in figure 3 8 and figure 3 9 . figure 3 8 C r ead to precharge ( rl = 9 , al = 0, cl = 9 , t rtp = 4, t rp = 9 ) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d n o p a d d r e s s r e a d n o p a c t p r e n o p n o p b a n k a , c o l n d q s , d q s # d q n o p n o p n o p t 1 1 t 1 2 t 1 3 t 1 4 n o p b a n k a , ( o r a l l ) n o p n o p n o p n o p d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 t r t p d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d q s , d q s # d q b l 4 o p e r a t i o n : b l 8 o p e r a t i o n : t r p r l = a l + c l = 9 t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . r l = 9 ( c l = 9 , a l = 0 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . t h e e x a m p l e a s s u m e s t r a s . m i n i s s a t i s f i e d a t p r e c h a r g e c o m m a n d t i m e ( t 5 ) a n d t h a t t r c . m i n i s s a t i s f i e d a t t h e n e x t a c t i v e c o m m a n d t i m e ( t 1 4 ) . b a n k a , r o w b t 1 5 n o p
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 55 - figure 3 9 C read to precharge ( rl = 20 , al = cl - 2, cl = 11 , t rtp = 6, t rp = 11 ) t 0 t 1 t 2 t 1 0 t 1 1 t 1 6 t 1 8 t 1 9 t 2 0 t 2 1 t 2 2 c k # c k c o m m a n d n o p a d d r e s s r e a d n o p a c t p r e n o p n o p b a n k a , c o l n d q s , d q s # d q n o p n o p n o p t 2 3 t 2 4 t 2 5 t 2 7 n o p b a n k a , ( o r a l l ) n o p n o p n o p n o p d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d o u t n + 4 d o u t n + 5 d o u t n + 6 d o u t n + 7 c l = 1 1 d o u t n d o u t n + 1 d o u t n + 2 d o u t n + 3 d q s , d q s # d q b l 4 o p e r a t i o n : b l 8 o p e r a t i o n : t r p a l = c l - 2 = 9 t 2 6 n o p t r t p b a n k a , r o w b t r a n s i t i o n i n g d a t a d o n ' t c a r e n o t e s : 1 . r l = 2 0 ( c l = 1 1 , a l = c l - 2 ) 2 . d o u t n = d a t a - o u t f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . t h e e x a m p l e a s s u m e s t r a s . m i n i s s a t i s f i e d a t p r e c h a r g e c o m m a n d t i m e ( t 1 6 ) a n d t h a t t r c . m i n i s s a t i s f i e d a t t h e n e x t a c t i v e c o m m a n d t i m e ( t 2 7 ) . t i m e b r e a k r l = 2 0
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 56 - 8.14 write operation 8.14.1 ddr3l burst operation during a read or write command, ddr3l will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). a12 = 0, bc4 (bc4 = burst chop, t ccd = 4) a12 = 1, bl8 a12 is used only for burst length control, not as a column address . 8.14.2 write timing violations 8.14.2.1 motivation generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the dram works properly. however, it is desirable; for certain minor violations, that the dram is guaranteed not to hang up , and that errors are limited to that particular operation. fo r the following, it will be assumed that there are no timing violations with regards to the write command itself (including odt, etc.) and that it does satisfy all timing requirements not mentioned below. 8.14.2.2 data setup and hold violations should the data to s trobe timing requirements (t ds , t dh ) be violated, for any of the strobe edges associated with a write burst, and then wrong data might be written to the memory location addressed with this write command. in the example (figure 40 on page 5 7 ), the relevant strobe edges for write burst a are associated with the clock edges: t5, t5.5, t6, t6.5, t7, t7.5, t8, t8.5 . subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. 8.14.2.3 strobe to strobe and str obe to clock violations should the strobe timing requirements (t dqsh , t dqsl , t wpre , t wpst ) or the strobe to clock timing requirements (t dss , t dsh , t dqss ) be violated, for any of the strobe edges associated with a write burst, then wrong data might be writt en to the memory location addressed with the offending write command. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. in the example (figure 4 8 on page 6 1 ) the relevant strobe edge s for write burst n are associated with the clock edges: t4, t4.5, t5, t5.5, t6, t6.5, t7, t7.5, t8, t8.5 and t9. any timing requirements starting or ending on one of these strobe edges need to be fulfilled for a valid burst. for write burst b the relevant edges are t8, t8.5, t9, t9.5, t10, t10.5, t11, t11.5, t12, t12.5 and t13. some edges are associated withboth bursts. 8.14.2.4 write timing parameters this drawing is for example only to enumerate the strobe edges that belong to a write burst. no actual timing violations are shown here. for a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge - as shown).
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 57 - note s : 1. bl8, wl = 5 (al = 0, cwl = 5) 2. d in n = data - in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 a [1:0 ] = 00 or mr0 a [1:0 ] = 0 1 and a12 = 1 during write command at t0. 5. t dqss must be met at each rising clock edge. figure 40 C write timing definition and parameters 8.14.3 write data mask one write data mask (dm) pin for each 8 data bits (dq) will be supported on ddr3l sdrams, consistent with the implementation on ddr2 sdrams. it has identical timings on write operations as the data bit s as shown in figure 40 , and though used in a unidirectional manner, is internally loaded identically to data bits to ensure matched system timing. dm is not used during read cycles, however, dm can be used as tdqs during write cycles if enabled by the mr1 [a11] setting. see section 8 .3.2.7 tdqs, tdqs# on page 2 1 for more details on tdqs vs. dm operations . t r a n s i t i o n i n g d a t a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 a d d r e s s * 4 d o n ' t c a r e d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 6 d i n n + 7 t d q s s ( m i n ) b a n k c o l n w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p w l = a l + c w l d i n n d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 6 d i n n + 7 d i n n d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 6 d i n n + 7 d m d q s , d q s # d q * 2 d m d q s , d q s # d q d m t d q s s ( n o m i n a l ) t w p r e ( m i n ) t d q s s t d s h t d s h t d s h t d s h t w p s t ( m i n ) t d q s l t d q s h t d q s h ( m i n ) t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l ( m i n ) t d s s t d s s t d s s t d s s t d s s t w p r e ( m i n ) t d q s h ( m i n ) t d s h t d s h t d s h t d s h t w p s t ( m i n ) t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l ( m i n ) t d s s t d s s t d s s t d s s t d s s t w p r e ( m i n ) t d s h t d q s s t d s h t d s h t d s h t w p s t ( m i n ) t d q s h ( m i n ) t d s s t d s s t d s s t d s s t d s s t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l t d q s h t d q s l ( m i n ) t d q s s ( m a x )
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 58 - 8.14.4 t wpre calculation the method for calculating differential pulse widths for t wpre is shown in figure 4 1 . figure 4 1 C method for calculating t wpre transitions and endpoints 8.14.5 t wp st calculation the method for calculating differential pulse widths for t w p st is shown in figure 4 2 . figure 4 2 C method for calculating t wp st transitions and endpoints c k c k # d q s - d q s # r e s u l t i n g d i f f e r e n t i a l s i g n a l , r e l e v a n t f o r t w p r e s p e c i f i c a t i o n v t t 0 v t 1 t w p r e t w p r e _ b e g i n t 2 t w p r e _ e n d c k c k # d q s - d q s # r e s u l t i n g d i f f e r e n t i a l s i g n a l , r e l e v a n t f o r t w p s t s p e c i f i c a t i o n t 1 t w p s t t w p s t _ b e g i n t 2 t w p s t _ e n d 0 v v t t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 59 - note s : 1. bl8, wl = 5; al = 0, cwl = 5. 2. d in n = data - in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 a [1:0 ] = 00 or mr0 a [1:0 ] = 0 1 and a12 = 1 during write command at t0 . figure 4 3 C write burst operation w l = 5 (al = 0, c w l = 5, bl8) note s : 1. bl8, wl = 10 ; al = cl - 1 , cl = 6 , cwl = 5. 2. d in n = data - in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 a [1:0 ] = 00 or mr0 a [1:0 ] = 0 1 and a12 = 1 during write command at t0 . figure 4 4 C write burst operation w l = 10 (al = cl - 1 , c w l = 5, bl8) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 6 d i n n + 7 b a n k c o l n w r i t e n o p n o p n o p n o p t w p r e d i n n + 1 d i n n + 5 t w p s t n o p n o p n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e w l = a l + c w l t 0 t 1 t 5 t 6 t 9 t 1 0 t 1 1 t 1 2 t 1 3 t 1 4 t 1 5 c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 d i n n + 4 d i n n + 6 d i n n + 7 b a n k c o l n w r i t e n o p n o p n o p n o p a l = 5 t w p r e d i n n + 1 d i n n + 5 t w p s t n o p n o p n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e c w l = 5 w l = a l + c w l t i m e b r e a k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 60 - note s : 1. bc4, wl = 5, rl = 6 . 2. d in n = data - in from column n; d out b = data - out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 a [1:0 ] = 1 0 during write command at t0 and read command at tn. 5. t wtr controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at t7 . figure 4 5 C write (bc4) to read (bc4) operation note s : 1. bc4, wl = 5, rl = 6 . 2. d in n = data - in from column n; d out b = data - out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 a [1:0 ] = 1 0 during write command at t0. 5. the write recovery time (t wr ) refer enced from the first rising clock edge after the last write data shown at t7. t wr specifies the last burst write cycle until the precharge command can be issued to the same bank . figure 4 6 C write (bc4) to precharge operation t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t n c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 b a n k c o l a w r i t e n o p n o p n o p n o p n o p n o p n o p r e a d w l = 5 t w p r e d i n n + 1 t w p s t n o p n o p t w t r * 5 b a n k c o l b r l = 6 t i m e b r e a k t r a n s i t i o n i n g d a t a d o n ' t c a r e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t n c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 b a n k c o l n w r i t e n o p n o p n o p n o p n o p n o p n o p p r e w l = 5 t w p r e d i n n + 1 t w p s t n o p n o p t w r * 5 t i m e b r e a k t r a n s i t i o n i n g d a t a d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 61 - figure 4 7 C write (bc4) otf to precharge operation figure 4 8 C write (bl8) to write (bl8) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 b a n k c o l a w l = 5 t w p r e d i n n + 1 t w p s t 4 c l o c k s v a l i d t a 0 t 1 1 t a 1 t 1 4 t w r * 5 n o t e s : 1 . b c 4 o n t h e f l y , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 o n t h e f l y s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) s t a r t s a t t h e r i s i n g c l o c k e d g e t 9 ( 4 c l o c k s f r o m t 5 ) . w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p p r e t r a n s i t i o n i n g d a t a d o n ' t c a r e t i m e b r e a k t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 d i n n d i n n + 2 d i n n + 3 b a n k c o l n w l = 5 t w p r e d i n n + 1 t w p s t 4 c l o c k s b a n k c o l b t 1 2 t 1 1 t 1 3 t 1 4 t w r t w t r w l = 5 t c c d d i n n + 5 d i n n + 6 d i n n + 4 d i n b d i n b + 1 d i n n + 7 d i n b + 3 d i n b + 4 d i n b + 2 d i n b + 6 d i n b + 7 d i n b + 5 n o t e s : 1 . b l 8 , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 a [ 1 : 0 ] = 0 0 o r m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 a n d t 4 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) a n d w r i t e t i m i n g p a r a m e t e r ( t w t r ) a r e r e f e r e n c e d f r o m t h e f i r s t r i s i n g c l o c k e d g e a f t e r t h e l a s t w r i t e d a t a s h o w n a t t 1 3 . w r i t e n o p n o p n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 62 - figure 4 9 C write (bc4) to write (bc4) otf figure 50 C write (bl8) to read (bc4/bl8) otf d i n n d i n n + 2 d i n n + 3 w l = 5 t w p r e d i n n + 1 t w p s t w l = 5 d i n b d i n b + 1 d i n b + 3 d i n b + 2 t w p r e t w p s t t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 4 c l o c k s t 1 2 t 1 1 t 1 3 t 1 4 t w r t w t r t c c d n o t e s : 1 . b c 4 , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 a n d t 4 . 5 . t h e w r i t e r e c o v e r y t i m e ( t w r ) a n d w r i t e t i m i n g p a r a m e t e r ( t w t r ) a r e r e f e r e n c e d f r o m t h e f i r s t r i s i n g c l o c k e d g e a t t 1 3 ( 4 c l o c k s f r o m t 9 ) . c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 w r i t e n o p n o p n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e b a n k c o l b b a n k c o l n t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 d i n n d i n n + 2 d i n n + 3 w l = 5 t w p r e d i n n + 1 t w p s t t w t r t 1 2 t 1 1 t 1 3 t 1 4 d i n n + 5 d i n n + 6 d i n n + 4 d i n n + 7 r l = 6 n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n ; d o u t b = d a t a - o u t f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y e i t h e r m r 0 a [ 1 : 0 ] = 0 0 o r m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . r e a d c o m m a n d a t t 1 3 c a n b e e i t h e r b c 4 o r b l 8 d e p e n d i n g o n m r 0 a [ 1 : 0 ] a n d a 1 2 s t a t u s a t t 1 3 . c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e b a n k c o l b b a n k c o l n
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 63 - figure 5 1 C write (bc4) to read (bc4/bl8) otf figure 5 2 C write (bc4) to read (bc4) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 d i n n d i n n + 2 w l = 5 t w p r e d i n n + 1 t w p s t t w t r t 1 2 t 1 1 t 1 3 t 1 4 d i n n + 3 r l = 6 n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n ; d o u t b = d a t a - o u t f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 . r e a d c o m m a n d a t t 1 3 c a n b e e i t h e r b c 4 o r b l 8 d e p e n d i n g o n m r 0 a [ 1 : 0 ] a n d a 1 2 s t a t u s a t t 1 3 . c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e b a n k c o l b b a n k c o l n 4 c l o c k s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 d i n n d i n n + 2 w l = 5 t w p r e d i n n + 1 t w p s t t w t r t 1 2 t 1 1 t 1 3 t 1 4 d i n n + 3 r l = 6 n o t e s : 1 . r l = 6 ( c l = 6 , a l = 0 ) , w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n = d a t a - i n f r o m c o l u m n n ; d o u t b = d a t a - o u t f r o m c o l u m n b . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 1 0 . c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p r e a d n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e b a n k c o l b b a n k c o l n
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 64 - figure 5 3 C write (bl8) to write (bc4) otf figure 5 4 C write (bc4) to write (bl8) otf t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 d i n n d i n n + 2 d i n n + 3 w l = 5 t w p r e d i n n + 1 t w p s t 4 c l o c k s t 1 2 t 1 1 t 1 3 t 1 4 d i n n + 5 d i n n + 6 d i n n + 4 d i n b + 3 t w t r n o t e s : 1 . w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 0 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 4 . c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 w r i t e n o p n o p n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e b a n k c o l b b a n k c o l n d i n n + 7 d i n b + 1 d i n b + 2 d i n b t w r w l = 5 t c c d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 d i n n d i n n + 2 d i n n + 3 w l = 5 t w p r e d i n n + 1 t w p s t 4 c l o c k s t 1 2 t 1 1 t 1 3 t 1 4 d i n b + 1 d i n b + 2 d i n b d i n b + 7 t w t r n o t e s : 1 . w l = 5 ( c w l = 5 , a l = 0 ) 2 . d i n n ( o r b ) = d a t a - i n f r o m c o l u m n n ( o r c o l u m n b ) . 3 . n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s . 4 . b c 4 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 0 d u r i n g w r i t e c o m m a n d a t t 0 . b l 8 s e t t i n g a c t i v a t e d b y m r 0 a [ 1 : 0 ] = 0 1 a n d a 1 2 = 1 d u r i n g w r i t e c o m m a n d a t t 4 . c k # c k c o m m a n d * 3 a d d r e s s * 4 d q s , d q s # d q * 2 w r i t e n o p n o p n o p n o p w r i t e n o p n o p n o p n o p n o p n o p n o p n o p n o p t r a n s i t i o n i n g d a t a d o n ' t c a r e b a n k c o l b b a n k c o l n d i n b + 3 d i n b + 5 d i n b + 6 d i n b + 4 t w r w l = 5 t c c d t w p r e t w p s t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 65 - 8.15 refresh command the refresh command (ref) is used during normal operation of the ddr3l sdrams. this command is non persistent, so it must be issued each time a refresh is required. the ddr3l sdram requires refresh cycles at an average periodic interval of t refi . when cs#, ras# and cas# are held low and we# high at the rising edge of the clock, the chip enters a ref resh cycle. all banks of the sdram must be precharged and idle for a minimum of the precharge time t rp (min) before the refresh command can be applied. the refresh addressing is generated by the internal refresh controller. this makes the address bits d on' t c are during a refresh command. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the refresh command and the next valid command, except nop or des, must be greater than or equal to the minimum refresh cycle time t rfc (min) as shown in figure 5 5 . note that the t rfc timing parameter depe nds on memory density. in general, a refresh command needs to be issued to the ddr3l sdram regularly every t refi interval. to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is pro vided. a maximum of 8 refresh commands can be postponed during operation of the ddr3l sdram, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the r esulting maximum interval between the surrounding refresh commands is limited to 9 t refi (see figure 5 6 ). a maximum of 8 additional refresh commands can be issued in advance (pulled in), with each one reducing the number of regular refresh commands req uired later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 t refi (see figure 5 7 ). at any given time, a maximum of 16 ref commands can be issued within 2 x t refi . self - refresh mode may be entered with a maximum of eight refresh commands being postponed. after exiting self - refresh mode with one or more refresh com mands postponed, additional refresh commands may be postponed to the extent that the total number of postponed refresh commands (before and after the self - refresh) will never exceed eight. during self - refresh mode, the number of postponed or pulled - in ref commands does not change . figure 5 5 C refresh command timing t i m e b r e a k d o n ' t c a r e d r a m m u s t b e i d l e d r a m m u s t b e i d l e n o t e s : 1 . o n l y n o p / d e s c o m m a n d s a l l o w e d a f t e r r e f r e s h c o m m a n d r e g i s t e r e d u n t i l t r f c ( m i n ) e x p i r e s . 2 . t i m e i n t e r v a l b e t w e e n t w o r e f r e s h c o m m a n d s m a y b e e x t e n d e d t o a m a x i m u m o f 9 x t r e f i . t 0 t 1 t a 0 t a 1 t b 0 t b 1 t b 2 t b 3 c k # c o m m a n d r e f n o p n o p r e f n o p v a l i d n o p t c 1 t c 0 t c 2 t c 3 n o p t r f c v a l i d r e f v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d t r f c ( m i n ) t r e f i ( m a x . 9 x t r e f i ) c k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 66 - figure 5 6 C postponing refresh commands (example) figure 5 7 C pulling - in refresh commands (example) t r f c 8 r e f - c o m m a n d s p u l l e d - i n t r e f i 9 x t r e f i t t r f c 8 r e f - c o m m a n d s p u l l e d - i n t r e f i 9 x t r e f i t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 67 - 8.16 self - refresh operation the self - refresh command can be used to retain data in the ddr3l sdram, even if the rest of the system is powered down. when in the self - refresh mode, the ddr3l sdram retains data without external clocking. the ddr3l sdram device has a built - in timer to accommodate self - refresh operation. the self - refresh - entry (sre) command is defined by having cs#, ras#, cas#, and cke held low with we# high at the rising edge of the clock. before issuing the self - refresh - entry command, the ddr3l sdram must be idle with all bank precharge state with t rp satisfied. idle state is defined as all banks are closed (t rp , t dal , etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (t mrd , t m od , t rfc , t zq init, t zq oper, t zqcs , etc.) also, on - die termination must be turned off before issuing self - refresh - entry command, by either registering odt pin low odtl + 0.5t ck prior to the self - refresh entry command or using mrs to mr1 command. once the self - refresh entry command is registered, cke must be held low to keep the device in self - refresh mode. during normal operation (dll on), mr1 (a0 = 0), the dll is automatically disabled upon entering self - refresh and is automatically enabled (including a d ll - reset) upon exiting self - refresh. when the ddr3l sdram has entered self - refresh mode, all of the exter nal control signals, except cke and reset#, are d on't care . for proper self - refresh operation, all power supply and reference pins (v dd , v ddq , v ss , v ssq , v r ef ca and v r ef dq ) must be at valid levels. v refdq supply may be turned off and v refdq may take any value between v ss and v dd during self refresh operation, provided that v ref dq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh . the dram initiates a minimum of one refresh command internally within t cke period once it enters self - refresh mode. the clock is internally disable d during self - refresh operation to save p ower. the minimum time that the ddr3l sdram must remain in self - refresh mode is t cke sr . the user may change the external clock frequency or halt the external clock t cksre after self - refresh entry is regi stered, howe ver, the clock must be restarted and stable t cksrx before the device can exit self - refresh operation. the procedure for exiting self - refresh requires a sequence of events. first, the clock must be stable prior to cke going back high. once a self - refresh exit command (srx, combination of cke going high and either nop or deselect on command bus) is registered, a delay of at least t xs must be satisfied before a valid command not requiring a locked dll can be issued to the device to allow for any internal ref resh in progress. before a command that requires a locked dll can be applied, a delay of at least t xsdll must be satisfied. depending on the system environment and the amount of time spent in self - refresh, zq calibration commands may be required to compensate for the voltage and temperature drift as described in section 8 .18 zq calibration commands on page 7 7 . to issue zq calibration commands, applicable timing requirements must be satisfied (see figure 7 2 - zq calibration timing on page 7 8 ). cke must remain high for the entire self - refre sh exit period t xsdll for proper operation except for self - refresh re - entry. upon exit from self - refresh, the ddr3l sdram can be put back into self - refresh mode after waiting at least t xs period and issuing one refresh command (refresh period of t rfc ). nop or deselect commands must be registered on each positive clock edge during the self - refresh exit interval t xs . odt must be turned off during t xsdll .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 68 - the use of self - refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self - refresh mode. upon exit from self - refresh, the ddr3l sdram requires a minimum of one extra refresh command before it is put back into self - refresh mode. note s : 1. only nop or des command. 2. valid commands not requiring a locked dll. 3. valid commands requiring a locked dll . figure 5 8 C self - refresh entry/exit timing t 0 t 1 t 2 t a 0 t b 0 t c 0 t c 1 t d 0 c k # c k c o m m a n d t f 0 t e 0 v a l i d v a l i d v a l i d n o p s r e n o p n o p * 1 v a l i d * 2 v a l i d * 3 s r x v a l i d v a l i d t r p o d t l t x s d l l t x s t i s t i s t c p d e d t c k e s r t c k s r e t c k s r x e n t e r s e l f r e f r e s h e x i t s e l f r e f r e s h c k e o d t a d d r e s s t i m e b r e a k d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 69 - 8.17 power - down modes 8.17.1 power - down entry and exit power - down is synchronously entered when cke is registered low (along with nop or deselect command). cke is not allowed to go low while mode register set command, mpr operations, zqcal operations, dll locking or read / write operation are in progress. cke is allowed to go low while any of other operations such as row activation, precharge or auto - precharge and refresh are in progress, but power - down i dd spec will not be applied until finishing those operations. timing diagrams are shown in figure 5 9 through figure 7 1 with details for entry and exit of power - down. the dll should be in a locked state when power - down is entered for fastest power - down exit timing. if the dll is not locked during power - down entry, the dll must be reset after exiting power - down mode for proper read operation and synchronous odt operation. dram design pro vides all ac and dc timing and voltage specification as well as proper dll operation with any cke intensive operations as long as dram controller complies with dram specifications. during power - down, if all banks are closed after any in - progress commands a re completed, the device will be in precharge power - down mode; if any bank is open after in - progress commands are completed, the device will be in active power - down mode. entering power - down deactivates the input and output buffers, excluding ck, ck#, odt, cke and reset#. to protect dram internal delay on cke line to block the input signals, multiple nop or deselect commands are needed during the cke switch off and cycle(s) after, this timing period are defined as t cpded . cke_low will result in deactivation of command and address receivers after t cpded has expired. table 8 C power - down entry definitions status of dram mrs bit a12 dll pd exit relevant parameters active (a bank or more open) don't care on fast txp to any valid command precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands here will be act, ref, mrs, pre or prea. txpdll to commands that need the dll to operate, such as rd, rda or odt control line. precharged (all banks precharged) 1 on fast txp to any valid command also, the dll is disabled upon entering precharge power - down (slow exit mode), but the dll is kept enabled during precharge power - down (fast exit mode) or active power - down. in power - down mode, cke low, reset# high, and a stable clock signal must be maint ained at the inputs of the ddr3l sdram, and odt should be in a valid state, but all other input signals are d on't c are . (if reset# goes low during power - down, the dram will be out of pd mode and into reset state.) cke low must be maintained until t cke has been satisfied. power - down duration is limited by 9 times t refi of the device. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect command). cke high must be maintained u ntil t cke has been satisfied. a valid, executable command can be applied with power - down exit latency, t xp and/or t xpdll after cke goes high. power - down exit latency is defined in section 10 .1 6 ac characteristics on page 1 3 7 . active power down entry and exit timing diagram example is shown in figure 5 9 . timing diagrams for cke with pd entry, pd exit with read and read with auto pr echarge, write, write with auto precharge, activate, precharge, refresh, and mrs are shown in figure 60 through figure 6 8 . additional clarifications are shown in figure 6 9 through figure 7 1 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 70 - note: 1. valid command at t0 is act, nop, des or pre with still one bank remaining open after completion of the precharge command. figure 5 9 C active power - down entry and exit timing diagram figure 60 C power - down entry after read and read with auto precharge t 0 t 1 t 2 t a 0 t b 0 t b 1 t c 0 c k # c k v a l i d n o p n o p t i s t a 1 n o p n o p n o p v a l i d v a l i d v a l i d v a l i d v a l i d t i h t i h t i s t x p t c k e t c p d e d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t p d c o m m a n d c k e a d d r e s s t i m e b r e a k d o n ' t c a r e t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t a 7 t a 8 c k # c k c o m m a n d a d d r e s s d q s , d q s # d q b l 8 d o u t b d o u t b + 2 d o u t b + 3 v a l i d r d o r r d a n o p n o p n o p n o p d o u t b + 1 t c p d e d t b 1 t b 0 n o p n o p v a l i d d o u t b + 5 d o u t b + 6 d o u t b + 4 d o u t b + 7 n o p d o u t b + 1 d o u t b + 2 d o u t b d o u t b + 3 n o p n o p n o p n o p v a l i d v a l i d t i s t p d r l = a l + c l t r d p d e n d q b c 4 t i m e b r e a k t r a n s i t i o n i n g d a t a d o n ' t c a r e p o w e r - d o w n e n t e r y c k e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 71 - note: 1. t wr is programmed through mr0 . figure 6 1 C power - down entry after write with auto precharge figure 6 2 C power - down entry after write t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t a 7 t b 2 c k # c k c o m m a n d a d d r e s s d i n b d i n b + 2 d i n b + 3 b a n k c o l n w r i t e n o p n o p n o p n o p d i n b + 1 t c p d e d t b 1 t b 0 n o p n o p n o p d i n b + 5 d i n b + 6 d i n b + 4 d i n b + 7 n o p d i n b + 1 d i n b + 2 d i n b d i n b + 3 n o p n o p n o p n o p t i s t p d w l = a l + c w l t w r a p d e n t c 0 t c 1 n o p w r * 1 v a l i d v a l i d v a l i d t i m e b r e a k t r a n s i t i o n i n g d a t a d o n ' t c a r e p o w e r - d o w n e n t e r y d q s , d q s # d q b l 8 d q b c 4 s t a r t i n t e r n a l p r e c h a r g e a 1 0 c k e t 0 t 1 t a 0 t a 1 t a 2 t a 3 t a 4 t a 5 t a 6 t a 7 t b 2 c k # c k c o m m a n d a d d r e s s d i n b d i n b + 2 d i n b + 3 b a n k c o l n w r i t e n o p n o p n o p n o p d i n b + 1 t c p d e d t b 1 t b 0 n o p n o p n o p d i n b + 5 d i n b + 6 d i n b + 4 d i n b + 7 n o p d i n b + 1 d i n b + 2 d i n b d i n b + 3 n o p n o p n o p n o p t i s t p d w l = a l + c w l t w r p d e n t c 0 t c 1 n o p t w r v a l i d v a l i d v a l i d t i m e b r e a k t r a n s i t i o n i n g d a t a d o n ' t c a r e p o w e r - d o w n e n t e r y d q s , d q s # d q b l 8 d q b c 4 a 1 0 c k e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 72 - figure 6 3 C precharge power - down (fast exit mode) entry and exit figure 6 4 C precharge power - down (slow exit mode) entry and exit t 0 t 1 t 2 t a 0 t b 0 t b 1 t c 0 c k # c k n o p n o p t i s t a 1 n o p n o p n o p v a l i d v a l i d v a l i d t i h t i s t x p t c k e t c p d e d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t p d c o m m a n d c k e t i m e b r e a k d o n ' t c a r e v a l i d t 0 t 1 t 2 t a 0 t b 0 t b 1 t c 0 c k # c k n o p n o p t i s t a 1 n o p n o p n o p v a l i d v a l i d t i h t i s t x p t c k e t c p d e d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t p d c o m m a n d c k e v a l i d v a l i d v a l i d t x p d l l t d 0 t i m e b r e a k d o n ' t c a r e v a l i d
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 73 - figure 6 5 C refresh command to power - down entry figure 6 6 C active command to power - down entry t 0 t 1 t 2 t a 0 c k # r e f n o p t a 1 n o p v a l i d v a l i d t p d t r e f p d e n t i s t c p d e d c o m m a n d a d d r e s s v a l i d n o p t 3 v a l i d c k e c k t i m e b r e a k d o n ' t c a r e v a l i d v a l i d t 0 t 1 t 2 t a 0 c k # a c t i v e n o p t a 1 n o p v a l i d v a l i d t p d t a c t p d e n t i s t c p d e d c o m m a n d a d d r e s s v a l i d n o p t 3 v a l i d c k e c k t i m e b r e a k d o n ' t c a r e v a l i d v a l i d
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 74 - figure 6 7 C precharge / precharge all command to power - down entry figure 6 8 C mrs command to power - down entry t 0 t 1 t 2 t a 0 c k # p r e o r p r e a n o p t a 1 n o p v a l i d v a l i d t p d t p r e p d e n t i s t c p d e d c o m m a n d a d d r e s s v a l i d n o p t 3 v a l i d c k e c k t i m e b r e a k d o n ' t c a r e v a l i d v a l i d t 0 t 1 t a 0 t b 0 m r s n o p t b 1 n o p v a l i d v a l i d t p d t m r s p d e n t i s t c p d e d c o m m a n d a d d r e s s v a l i d n o p t a 1 v a l i d c k e c k # c k t i m e b r e a k d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 75 - 8.17.2 power - down clarifications - case 1 when cke is registered low for power - down entry, t pd (min) must be satisfied before cke can be registered high for power - down exit. the minimum value of parameter t pd (min) is equal to the minimum value of parameter t cke (min) as shown in section 10 .1 6 ac characteristics on page 1 3 7 . a detailed example of case 1 is shown in figure 6 9 . figure 6 9 C power - down entry/exit c larifications - case 1 8.17.3 power - down clarifications - case 2 for certain cke intensive operations, for example, repeated pd exit - refresh - pd entry sequences, the number of clock cycles between pd exit and pd entry may be insufficient to keep the dll updated. therefore, the following conditions must be met in addition to t cke in order to maintain proper dram operation when the refresh command is issued between pd exit and pd entry. power - down mode can be used in conjunction with the refresh command if the following conditions are met: 1) t xp must be satisfied before issuing the command. 2) t xpdll must be satisfied (referenced to the registration of pd exit) before the next power - down can be entered. a detailed example o f case 2 is shown in figure 70 . figure 70 C power - down entry/exit clarifications - case 2 t 0 t 1 t 2 t a 0 t b 0 t b 1 t b 2 c k # c k v a l i d n o p n o p t i s t a 1 n o p n o p n o p v a l i d v a l i d t i h t i h t i s t c p d e d t c k e t c p d e d e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t p d c o m m a n d c k e a d d r e s s t i m e b r e a k d o n ' t c a r e t i s e n t e r p o w e r - d o w n m o d e t 0 t 1 t 2 t a 1 c k # c k v a l i d n o p t b 0 n o p n o p n o p t x p d l l c o m m a n d n o p t a 0 c k e t b 1 t c 0 r e f a d d r e s s v a l i d t c p d e d e x i t p o w e r - d o w n m o d e e n t e r p o w e r - d o w n m o d e t i h t i s t i h t i s t p d t c 1 t d 0 n o p n o p t x p t c k e e n t e r p o w e r - d o w n m o d e t i m e b r e a k d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 76 - 8.17.4 power - down clarifications - case 3 if an early pd entry is issued after a refresh command, once pd exit is issued, nop or des with cke high must be issued until t rfc (min) from the refresh command is satisfied. this means cke can not be registered low twice within a t rfc (min) window. a detailed example of case 3 is shown in figure 7 1 . figure 71 C power - down entry/exit clarifications - case 3 t 0 t 1 t 2 t a 1 c k # c k r e f n o p t b 0 n o p n o p n o p t r f c ( m i n ) c o m m a n d n o p t a 0 c k e t b 1 t c 0 r e f a d d r e s s t c p d e d e x i t p o w e r - d o w n m o d e e n t e r p o w e r - d o w n m o d e t i h t i s t i h t i s t p d t c 1 t d 0 n o p n o p t x p t c k e e n t e r p o w e r - d o w n m o d e t i m e b r e a k d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 77 - 8.18 zq calibration commands 8.18.1 zq calibration description zq calibration command is used to calibrate dram r on & odt values over pvt (process, voltage and temperature). an external resistor (r zq ) between the dram zq pin and ground is used as a calibration reference. ddr3l sdram needs longer time to calibrate output driver and on - die termination circuits after power - up and/or any reset, medium time for a full calibration during normal operation (e.g. after self - refresh exit) and relatively smaller time to pe rform periodic update calibrations. zqcl (zq calibration long) command is used to perform the initial calibration during power - up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl co mmand triggers the calibration engine inside the dram and, once calibration is achieved, the calibrated values are transferred from the calibration engine to dram io, which gets reflected as updated output driver and on - die termination values. the first zq cl command issued after reset is allowed a timing period of t zq init to perform the full calibration and the transfer of values. all other zqcl commands except the first zqcl command issued after reset are allowed a timing period of t zq oper. zqcs (zq calibr ation short) command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter t zqcs . one zqcs command ca n effectively correct a minimum of 0.5 % (zq correction) of r on and r tt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the output driver voltage and temperature sensitivity and odt voltage and temperature sensitivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application - specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/ ? c , vsens = 0.15%/ mv, tdriftrate = 1 ? c /sec and vdriftrate = 15 mv/sec, then the interval between zqcs commands is calculated as: = 0.133 128ms no other activities should be performed on the dram channel by the controller for the duration of t zq init, t zq oper, or t zqcs . the quiet time on the dram channel allows accurate calibration of output driver and on - die termination values. once dram calibration is achieved, the dram should disable zq current consumption path to reduce power. all banks must be precharged and t rp met before zqcl or zqcs commands are issued by the controller. see section 9 .1 command truth table on p age 9 4 for a description of the zqcl and zqcs commands . zq calibration commands can also be issued in parallel to dll lock time w hen coming out of self refresh. upon self - refresh exit, d dr3l sdram will not perform an io calibration without an explicit zq calibration command. the earliest possible time for zq calibration command ( zqcs or zqcl ) after self refresh exit is t xs . in systems that share the zq resistor between devices, the controller must not allow any overlap of t zq oper, t zq init, or t zqcs between the devices. ) vdriftrate (vsens + ) tdriftrate (tsens on zqcorrecti 15) (0.15 + 1) (1.5 0.5
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 78 - 8.18.2 zq calibration timing note s : 1. cke must be continuously registered high during the calibration procedure. 2. on - die termination must be disabled via the odt signal or mrs during the calibration procedure. 3. all devices connected to the dq bus should be high impedance during the calibration procedure . figure 7 2 C zq calibration timing 8.18.3 zq external resistor value, tolerance, and capacitive loading in order to use the zq calibration function, a 240 ohm 1% tolerance external resistor must be connected between the zq pin and ground. the single resistor can be used for each sdram or one resistor can be shared between two sdrams if the zq calib ration timings for each sdram do not overlap. the total capacitive loading on the zq pin must be limited ( see section 10 .11 input/output capacitance on page 1 1 9 ). t 0 t 1 t a 1 c k # c k z q c l n o p t a 3 n o p v a l i d z q c s c o m m a n d v a l i d t a 0 a 1 0 t b 1 t c 0 n o p a d d r e s s t z q i n i t o r t z q o p e r t c 1 t c 2 n o p n o p t a 2 t b 0 v a l i d n o p v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d c k e o d t h i - z a c t i v i t i e s h i - z v a l i d v a l i d v a l i d v a l i d a c t i v i t i e s d q b u s t z q c s t i m e b r e a k d o n ' t c a r e * 1 * 2 * 3 * 1 * 2 * 3
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 79 - 8.19 on - die termination (odt) odt (on - die termination) is a feature of the ddr3l sdram that allows the dram to turn on/off termination resistance for each dq, dqs, dqs# and dm (and tdqs, tdqs#, when enabled via a11=1 in mr1) signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. more details about odt control modes an d odt timing modes can be found further down in this document: ? the odt control modes are described in section 8.19.1 ? the odt synchronous mode is described in sectio n 8.19.2 ? the dynamic odt feature is described in section 8.19.3 ? the odt asynchronous mode is described in section 8.19.4 ? the transitions between odt synchronous a nd asynchronous are described in section 8.19.4.1 through section 8.19.4.4 the odt feature is turned off and not supported in self - refresh mode. a simple functional representation of the dram odt feature is shown in figure 7 3 . figure 7 3 C functional representation of odt the switch is enabled by the internal odt control logic, which uses the external odt pin and other control information, see below. the value of r tt is determined by the settings of mode register bits ( s ee figure 6 - mr 1 definition and figure 7 - mr2 definition ). the odt pin will be ignored if the mode registers mr1 and mr2 are programmed to disable odt, and in self - refresh mode. 8.19.1 odt mode register and odt truth table the odt mode is enabled if any of mr1 {a9, a6, a2} or mr2 {a10, a9} are non zero. in this case, the value of r tt is determined by the settings of those bits ( see figure 6 on page 1 9 ). application: controller sends wr command together with odt asserted. ? one possible application: the rank that is being written to provides termination. ? dram turns on termination if it sees odt asserted (unless odt is disabled by mr). ? dram does not use any write or read command decode information. ? the termination truth table is shown in table 9 . table 9 C termination truth table odt pin dram termination state 0 off 1 on, (off, if disabled by mr1 {a9, a6, a2} and mr2 {a10, a9} in general) v d d q / 2 s w t i c h o d t r t t t o o t h e r c i r c u i t r y l i k e r c v , d q , d q s , d m , t d q s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 80 - 8.19.2 synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power - down definition, these modes are: ? any bank active with cke high ? refresh with cke high ? idle mode with cke high ? active power down mode (regardless of mr0 bit a12) ? precharge power down mode if dll is enabled during precharge power down by mr0 bit a12. the direct odt feature is not supported during dll - off mode. the on - die termination resistor s must be disabled by continuously registering the odt pin low and/or by programming the r tt _nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll - off mode. in synchronous odt mode, r tt will be turned on odtlon clock cycles after odt is sampled high by a rising clock edge and turned off odtloff clock cycles after odt is registered low by a rising clock edge. the odt latency is tied to the write latency (wl) by: odtlon = wl - 2; odtloff = wl - 2. 8.19.2.1 odt latency and posted odt in synchron ous odt mode, the additive latency (al) programmed into the mode register (mr1) also applies to the odt signal. the dram internal odt signal is delayed for a number of clock cycles defined by the additive latency (al) relative to the external odt signal. o dtlon = cwl + al - 2; odtloff = cwl + al - 2. for more details refer to the odt t iming p arameters in section 10 .1 6 ac characteristics on page 1 3 7 . table 10 C odt latency symbol parameter ddr3l - 1333/1600/1866 unit odtlon odt turn on latency wl - 2 = cwl + al - 2 n ck odtloff odt turn off latency wl - 2 = cwl + al - 2 8.19.2.2 timing parameters in synchronous odt mode, the following timing param eters apply (see also figures 7 4 ): odtlon, odtloff, t aon ,min,max, t aof ,min,max. minimum r tt turn - on time (t aon min) is the point in time when the d evice leaves high impedance and odt resistance begins to turn on. maximum r tt turn on time (t aon max) is the point in time when the odt resistance is fully on. both are measured from odtlon. minimum r tt turn - off time (t aof min) is the point in time when the de vice starts to turn off the odt resistance. maximum r tt turn off time (t aof max) is the point in time when the on - die te rmination has reached high impedance. both are measured from odtloff. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registere d by the sdram with odt high, then odt must remain high until odth4 (bl = 4) or odth8 ( bl = 8) after the write command (see figure 7 5 ). odth4 and odth8 are measured from odt registered high to odt registered low or from the registration of a write command until odt is registered low. odt must be held high for at least odth4 after assertion ( t1); odt must be kept high odth4 (bl = 4) or odt h8 (bl = 8) after write command (t7 ). odth is measured from odt first registered high to odt first registered low, or from registration of write command with odt high to odt registered low. note that although odth4 is satisfied from odt registered high at t6 , odt must not go low before t11 as odth4 must also be satisfied from the registration of the write command at t7 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 81 - figure 7 4 C sync hronous odt timing ( al = 3; cwl = 5; odtlon = al + cwl - 2 = 6 ; odtloff = al + cwl - 2 = 6 ) figure 7 5 C synchronous odt ( bl = 4, wl = 7 ) t 0 t 1 t 2 t 4 c k # c k t 5 t 3 o d t t 6 t 7 t a o n m i n t 8 t 9 t 1 0 t 1 2 t 1 3 t 1 4 t 1 5 t 1 1 a l = 3 o d t h 4 m i n o d t l o n = c w l + a l - 2 t a o n m a x r t t _ n o m t a o f m i n t a o f m a x o d t l o f f = c w l + a l - 2 a l = 3 c w l - 2 c k e d r a m _ r t t t r a n s i t i o n i n g d o n ' t c a r e t 0 t 1 t 2 t 4 c k # c k t 5 t 3 o d t t 6 t 7 t a o n m i n t 8 t 9 t 1 0 t 1 2 t 1 3 t 1 4 t 1 5 t 1 1 t a o n m a x r t t _ n o m t a o f m i n t a o f m a x c k e d r a m _ r t t n o p n o p w r s 4 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 1 6 t a o n m a x t a o n m i n t a o f m i n t a o f m a x c o m m a n d o d t h 4 o d t h 4 m i n o d t h 4 o d t l o n = w l - 2 o d t l o n = w l - 2 o d t l o f f = w l - 2 o d t l o f f = w l - 2 t r a n s i t i o n i n g d o n ' t c a r e t 1 7
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 82 - 8.19.2.3 odt during reads as the ddr3l sdram can not terminate and drive at the same time, r tt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. r tt may not be enabled until the end of the post - amble as shown in the example below. as shown in figure 7 6 below, at cycle t15, dram turns on the termination when it stops driving, which is determined by t hz . if dram stops driving early (i.e., t hz is early), then t aon min timing may apply. if dram stops driving late (i.e., t hz is late), then dram complies with t aon max timing. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example in figure 7 6 . figure 7 6 C odt must be disabled externally d uring reads by driving odt low. (cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtlon = cwl + al - 2 = 8; odtloff = cwl + al - 2 = 8) t 0 t 1 t 2 t 4 c k # c k t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 2 t 1 3 t 1 4 t 1 5 t 1 1 r e a d n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p t 1 6 t a o f m i n c o m m a n d o d t t l o f f = c w l + a l - 2 o d t l o n = c w l + a l - 2 r l = a l + c l v a l i d r t t _ n o m n o p t 1 7 n o p n o p n o p d o u t b d o u t b + 2 d o u t b + 3 d o u t b + 1 d o u t b + 5 d o u t b + 6 d o u t b + 4 d o u t b + 7 t a o f m a x t a o n m a x r t t _ n o m n o p n o p r t t d q s , d q s # d q t r a n s i t i o n i n g d o n ' t c a r e a d d r e s s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 83 - 8.19.3 dynamic odt in certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the ddr3l sdram can be changed without issuing an mrs command. this requirement is supported by the dynamic odt feature as described as follows: 8.19.3.1 functional description: the dynamic odt mode is enabled if bit (a9) or (a10) of mr2 i s set to 1. the function is described as follows: ? two r tt values are available: r tt _nom and r tt _wr. ? the value for r tt _nom is preselected via bits a[9,6,2] in mr1. ? the value for r tt _wr is preselected via bits a[10,9] in mr2. ? during operation without write commands, the termination is controlled as follows: ? nominal termination strength r tt _nom is selected. ? termination on/off timing is controlled via odt pin and latencies odtlon and odtloff. ? when a write command (wr, wra, wrs4, wrs8, wras4, wras8) is registered, and if dynamic odt is enabled, the termination is controlled as follows: ? a latency odtlcnw after the write command, termination strength r tt _wr is selected. ? a latency odtlcwn8 (for bl8, fixed by mrs or selected otf) or odtlcwn4 (for bc4, fixed by mrs or selected otf) after the write command, termination strength r tt _nom is selected. ? termination on/off timing is controlled via odt pin and odtlon, odtloff. table 1 1 shows latencies and timing parameters which are relevant for the on - die termination control in dynamic odt mode. the dynamic odt feature is not supported at dll - off mode. user must use mrs command to set rtt_wr, mr2{a10, a9}={0,0}, to disable dynamic odt externally. when odt is asserted, it must remain high until odth4 is satisfied. if a write command is registered by the sdram with odt high, then odt must remain high until odth4 (bl = 4) or odth8 (bl = 8) after the write command ( see figure 7 7 ). odth4 and odth8 are measured from odt registered high to odt registered low or from the regis tration of a write command until odt is registered low.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 84 - table 1 1 C latencies and timing parameters relevant for dynamic odt name and description abbr. defined from defined to definition for all ddr3l speed bins unit odt turn - on latency odtlo n registering external odt signal high t urning termination o n odtlo n = wl - 2 t ck odt turn - o ff latency odtlo ff registering external odt signal low t urning termination o ff odtlo ff = wl - 2 t ck odt latency for changing from rtt_nom to rtt_wr odtlc nw registering external write command c hange r tt strength from rtt_nom to rtt_wr odtlc nw = wl - 2 t ck odt latency for change from rtt_wr to rtt_nom (bl = 4) odtlcwn 4 registering external write command c hange r tt strength from rtt_wr to rtt_nom odtlcwn4 = 4 + odtloff t ck odt latency for change from rtt_wr to rtt_nom (bl = 8 ) odtlcwn 8 registering external write command c hange r tt strength from rtt_wr to rtt_nom odtlcwn 8 = 6 + odtloff t ck (avg) minimum odt high time after odt assertion odth4 registering odt high odt registered low odth4 = 4 t ck (avg) minimum odt high time after write (bl = 4) odth4 registering write with odt high odt registered low odth4 = 4 t ck (avg) minimum odt high time after write (bl = 8 ) odth 8 registering write with odt high odt registered low odth4 = 6 t ck (avg) r tt change skew t adc odtlcnw odtlcwn r tt valid t adc (min) = 0.3 * t ck (avg) t adc (max) = 0.7 * t ck (avg) t ck (avg) note: t aof nom and t adc nom are 0.5 t ck (effectively adding half a clock cycle to odtloff, odtcnw and odtlcwn) 8.19.3.2 odt timing diagrams the following pages provide exemplary timing diagrams as described in table 1 2 : table 1 2 C timing diagrams for dynamic odt figure and page description figure 7 7 on page 8 5 figure 77 , dynamic odt: behavior with odt being asserted before and after the write figure 7 8 on page 8 6 figure 78 , dynamic odt: behavior without write command, al = 0, cwl = 5 figure 7 9 on page 8 6 figure 79 , dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles figure 80 on page 8 7 figure 80 , dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al = 0, cwl = 5 figure 81 on page 8 7 figure 8 1 , dynamic odt: behavior with odt pin being asserted together with write command for a duration of 4 clock cycles
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 85 - figure 7 7 C dynamic odt: behavior with odt being asserted before and after the write t 0 t 1 t 2 t 4 c k # c k t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 2 t 1 3 t 1 4 t 1 5 t 1 1 n o p n o p n o p t 1 6 t a d c m i n a d d r e s s o d t l o f f o d t h 4 o d t l c n w r t t _ n o m n o p t 1 7 d i n b d i n b + 2 d i n b + 3 d i n b + 1 t a d c m a x v a l i d o d t h 4 t a o n m i n t a o n m a x o d t l o n o d t l c w n 4 t a d c m a x t a d c m i n t a o f m a x t a o f m i n w l w r s 4 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p r t t d q d q s , d q s # r t t _ w r r t t _ n o m t r a n s i t i o n i n g d o n ' t c a r e n o t e s : e x a m p l e f o r b c 4 ( v i a m r s o r o t f ) , a l = 0 , c w l = 5 . o d t h 4 a p p l i e s t o f i r s t r e g i s t e r i n g o d t h i g h a n d t o t h e r e g i s t r a t i o n o f t h e w r i t e c o m m a n d . i n t h i s e x a m p l e , o d t h 4 w o u l d b e s a t i s f i e d i f o d t w e n t l o w a t t 8 ( 4 c l o c k s a f t e r t h e w r i t e c o m m a n d ) .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 86 - note s : 1. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. 2. odt registered low at t5 would also be legal . figure 7 8 C dynamic odt: behavior without write command, al = 0, cwl = 5 note: 1. example for bl8 (via mrs or otf), al = 0, cwl = 5. in this example, odth8 = 6 is exactly satisfied. figure 7 9 C dynamic odt: behavior with odt pin bei ng assert ed together with write command for a duration of 6 clock cycles t a o f m a x t 0 t 1 t 2 t 4 c k # c k d o n ' t c a r e t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 1 v a l i d t r a n s i t i o n i n g t a o f m i n a d d r e s s r t t _ n o m o d t h 4 t a o n m i n t a o n m a x r t t o d t l o f f v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d v a l i d c o m m a n d d q d q s , d q s # o d t l o n t 0 t 1 t 2 t 4 c k # c k d o n ' t c a r e t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 1 n o p t r a n s i t i o n i n g t a o f m i n a d d r e s s r t t _ w r t a o f m a x o d t h 8 t a o n m i n t a d c m a x r t t o d t l o f f w r s 8 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p c o m m a n d d q d q s , d q s # d i n b d i n b + 2 d i n b + 3 d i n b + 1 d i n b + 5 d i n b + 6 d i n b + 4 d i n b + 7 w l o d t l c w n 8 o d t l o n v a l i d o d t l c n w
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 87 - note s : 1. odth4 is defined from odt registered high to odt registered low, so in this example, odth4 is satisfied. 2. odt registered low at t5 would also be legal . figure 80 C dynamic odt: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example for bc4 (via mrs or otf), al = 0, cwl = 5 note: 1. example for bc4 (via mrs or otf), al = 0, cwl = 5. in this example, odth4 = 4 is exactly satisfied . figure 8 1 C dynamic odt: behavior with odt pin being asserted together with write command for a duration of 4 clock cycles t 0 t 1 t 2 t 4 c k # c k d o n ' t c a r e t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 1 n o p t r a n s i t i o n i n g a d d r e s s r t t w r s 4 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p c o m m a n d d q d q s , d q s # v a l i d o d t l c n w r t t _ w r d i n b d i n b + 2 d i n b + 3 d i n b + 1 w l o d t l c w n 4 r t t _ n o m t a d c m a x t a d c m i n t a o f m i n t a o f m a x o d t h 4 t a o n m i n t a d c m a x o d t l o f f o d t l o n t 0 t 1 t 2 t 4 c k # c k d o n ' t c a r e t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 1 n o p t r a n s i t i o n i n g a d d r e s s r t t w r s 4 n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p c o m m a n d d q d q s , d q s # v a l i d o d t l c n w r t t _ w r d i n b d i n b + 2 d i n b + 3 d i n b + 1 w l o d t l c w n 4 t a o f m a x t a o f m i n o d t h 4 t a o n m i n t a d c m a x o d t l o f f o d t l o n
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 88 - 8.19.4 asynchronous odt mode asynchronous odt mode is selected when dram runs in dllon mode, but dll is temporarily disabled (i.e. frozen) in precharge power - down (by mr0 bit a12). based on the power down mode definitions, this is currently precharge power down mode if dll is disabled during precharge pow er down by mr0 bit a12. in asynchronous odt timing mode, internal odt command is not delayed by additive latency (al) relative to the external odt co mmand. in asynchronous odt mode, the following timing parameters apply (see figure 8 2 ): t aonpd , min , max, t ao fpd , min , max. minimum r tt turn - on time (t aonpd min) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on. maximum r tt turn on time (t aonpd max) is the point in time when the odt resistance is fully on. t aonpd min and t aonpd max are measured from odt being sampled high. minimum r tt turn - off time (t aofpd min) is the point in time when the devices termination circuit starts to turn off the odt resistance. maximum odt turn off time (t aofpd max) is t he point in time when the on - die termination has reached high impedance. t aofpd min and t aofpd max are measured from odt being sampled low . figure 8 2 C asynchronous odt timings on ddr3l sdram with fast odt transition: al is ignored in precharge power down, odt receiver remains active, however no read or write command can be issued, as the respective add/c md receivers may be disabled. table 1 3 C asynchronous odt timing parameters for all speed bins symbol description m in . max. unit t aonpd asynchronous r tt turn - on delay (power - down with dll frozen) 2 8.5 ns t ao f pd asynchronous r tt turn - off delay (power - down with dll frozen) 2 8.5 ns t 0 t 1 t 2 t 4 c k # c k t 5 t 3 o d t t 6 t 7 t 8 t 9 t 1 0 t 1 2 t 1 3 t 1 4 t 1 5 t 1 1 t 1 6 t 1 7 t a o n p d m i n t i h r t t t i s t a o n p d m a x r t t t a o f p d m i n t a o f p d m a x t i h t i s c k e t r a n s i t i o n i n g d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 89 - 8.19.4.1 synchronous to asynchronous odt mode transitions table 1 4 C odt timing parameters for power down (with dll frozen) entry and exit transition period description m in . max. odt to r tt turn - on delay min{ odtlon * t ck (avg) + t aon min; t aonpd min } max{ odtlon * t ck (avg) + t aon max; t aonpd max } min{ (wl - 2) * t ck (avg) + t aon min; t aonpd min } max{ (wl - 2) * t ck (avg) + t aon max; t aonpd max } odt to r tt turn - o ff delay min{ odtloff * t ck (avg) +t aof min; t aofpd min } max{ odtloff * t ck (avg) + t aof max; t aofpd max } min{ (wl - 2) * t ck (avg) +t aof min; t aofpd min } max{ (wl - 2) * t ck (avg) + t aof max; t aofpd max } t anpd wl - 1 8.19.4.2 synchronous to asynchronous odt mode transition during power - down entry if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is a transition period around power down entry, where the ddr3l sdram may show either synchronous or asynchronous odt behavior. the transition period is defined by the parameters t anpd and t cpded (min). t anpd is equal to (wl - 1) and is counted backwar ds in time from the clock cycle where cke is first registered low. t cpded (min) starts with the clock cycle where cke is first registered low. the transition period begins with the starting point of t anpd and terminates at the end point of t cpded (min), as s hown in figure 8 3 . if there is a refresh command in progress while cke goes low, then the transition period ends at the later one of t rfc (min) after the refresh command and the end point of t cpded (min), as shown in figure 8 4 . please note that the actual st arting point at t anpd is excluded from the transition period, and the actual end points at t cpded (min) and t rfc (min), respectively, are included in the transition period. odt assertion during the transition period may result in an r tt change as early as the smaller of t aonpd min and (odtlon * t ck (avg) + t aon min) and as late as the larger of t aonpd max and (odtlon * t ck (avg) + t aon max). odt de - assertion during the transition period may result in an r tt change as early as the smaller of t a ofpd min and (odtloff * t ck (avg) + t aof min) and as late as the larger of t aofpd max and (odtloff * t ck (avg) + t aof max). see table 1 4 . note that, if al has a large value, the range where r tt is uncertain becomes quite large. figure 8 3 shows the three different cases: odt_a, synchronous behavior before t anpd ; odt_b has a state change during the transition period; odt_c shows a state change after the transition period .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 90 - figure 8 3 C synchronous to asynchro nous transition during precharge power down (with dll frozen) entry (al = 0; cwl = 5; t anpd = wl - 1 = 4) t 0 t 1 t 2 t 4 c k # c k t 5 t 3 l a s t s y n c , o d t t 6 t 7 t 8 t 9 t 1 0 t 1 2 n o p t a o f m i n r t t t a o f m a x n o p n o p n o p n o p c o m m a n d t 1 1 r t t t a o f p d m i n r t t t a o f p d m a x n o p n o p n o p n o p n o p n o p t c p d e d t c p d e d m i n t a n p d o d t l o f f p d e n t r y t r a n s i t i o n p e r i o d t a o f p d m a x o d t l o f f + t a o f m i n o d t l o f f + t a o f m a x p d e n t r y t r a n s i t i o n p e r i o d t a o f p d m i n c k e r t t s y n c o r a s y n c , o d t r t t f i r s t a s y n c , o d t r t t t r a n s i t i o n i n g d a t a d o n ' t c a r e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 91 - figure 8 4 C synchronous to asynchronous transition after refresh command (al = 0; cwl = 5; t anpd = wl - 1 = 4) t 0 t 1 t 2 t 4 c k # c k t 5 t 3 c o m m a n d t 6 t 7 t 8 t 9 t 1 0 t 1 2 t 1 3 t a 0 t a 1 t 1 1 t a 2 t a 3 r t t c k e n o p n o p n o p n o p n o p n o p n o p r e f n o p r t t r t t t a o f p d m a x l a s t s y n c , o d t r t t s y n c o r a s y n c , o d t r t t f i r s t a s y n c , o d t t a o f p d m i n o d t l o f f + t a o f p d m a x t a o f p d m i n t r f c ( m i n ) o d t l o f f + t a o f p d m i n p d e n t r y t r a n s i t i o n p e r i o d t c p d e d m i n t a n p d o d t l o f f t a o f m a x t a o f m i n t r a n s i t i o n i n g d o n ' t c a r e t a o f p d m a x t i m e b r e a k r t t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 92 - 8.19.4.3 asynchronous to synchronous odt mode transition during power - down exit if dll is selected to be frozen in precharge power down mode by the setting of bit a12 in mr0 to 0, there is also a transit ion period around power down exit, where either synchronous or asynchronous response to a change in odt must be expected from the ddr3l sdram. this transition period starts t anpd before cke is first registered high, and ends t xpdll after cke is first registered high. t anpd is eq ual to (wl - 1) and is counted (backwards) from the clock cycle where cke is first registered high. odt assertion during the transition period may result in an r tt change as early as the smaller of t aonpd min and (odtlon*t ck (avg) + t aon min) and as late as the larger of t aonpd max and (odtlon*t ck (avg) + t aon max). odt de - assertion during the transition period may result in an rtt change as early as the smaller of t aofpd min and (odtloff*t ck (avg) + t aof min) and as late as the larger of t aofpd max and (odtloff*t ck (avg) + t aof max). see table 1 4 . note that, if al has a large value, the range where r tt is uncertain becomes quite large. figure 8 5 shows the three different cases: odt_c, asynchronous response before t anpd ; odt_b has a state change of odt during the trans ition period; odt_a shows a state change of odt after the transition period with synchronous response. figure 8 5 C asynchronous to synchronous transit ion during precharge power down (with dll frozen) exit (cl = 6; al = cl - 1; cwl = 5; t anpd = wl - 1 = 9) t 0 t 1 t 2 t a 1 c k # c k t a 2 t a 0 c o m m a n d t a 3 t a 4 t a 5 t a 6 t b 0 t b 2 t c 0 t c 1 t c 2 t b 1 t d 0 t d 1 r t t c k e n o p n o p n o p n o p n o p n o p n o p n o p n o p r t t r t t r t t l a s t s y n c , o d t r t t s y n c o r a s y n c , o d t r t t f i r s t a s y n c , o d t t a o f m i n o d t l o f f + t a o f m a x t a o f p d m i n o d t l o f f + t a o f m i n p d e x i t t r a n s i t i o n p e r i o d t x p d l l t a o f p d m a x t a o f p d m i n n o p n o p n o p n o p n o p t a o f m a x o d t l o f f t a o f p d m a x t r a n s i t i o n i n g d o n ' t c a r e t a n p d t i m e b r e a k
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 93 - 8.19.4.4 asynchronous to synchronous odt mode during short cke high and short cke low periods if the total time in precharge power down state or idle state is very short, the transition periods for pd entry and pd exit may overlap (see figure 8 6 ). in this case, the response of the ddr3l sdrams r tt to a change in odt state at the input may be synchronous or asynchronous from the start of the pd entry transition period to the end of the pd exit transition period (even if the e ntry period ends later than the exit period). if the total time in i dle state is very short, the transition periods for pd exit and pd entry may overlap. in this case the response of the ddr3l sdrams r tt to a change in odt state at the input may be synchronous or asynchronous from the start of the pd exit transition period to t he end of the pd entry transition period. note that in the bottom part of figure 8 6 it is assumed that there was no refresh comman d in progress when i dle state was entered . figure 8 6 C transition period for short cke cycles, entry and exit period overlapping (al = 0, wl = 5, t anpd = wl - 1 = 4) t 0 t 1 t 2 t 4 c k # c k t 5 t 3 c o m m a n d t 6 t 7 t 8 t 9 t 1 0 t 1 2 t 1 3 t 1 4 t 1 1 c k e n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p n o p r e f c k e t r f c ( m i n ) t a n p d p d e n t r y t r a n s i t i o n p e r i o d p d e x i t t r a n s i t i o n p e r i o d t a n p d s h o r t c k e l o w t r a n s i t i o n p e r i o d t a n p d s h o r t c k e h i g h t r a n s i t i o n p e r i o d t x p d l l t i m e b r e a k t r a n s i t i o n i n g d o n ' t c a r e t x p d l l
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 94 - 9. operation mode 9.1 command truth table notes 1, 2, 3 and 4 apply to the entire command truth table . note 5 a pplies to all read/write commands . [ba=bank address, ra=row address, ca=column address, bc # =burst chop, x=d on't c are , v=valid] table 1 5 C command truth table command abbr. cke cs # ras # cas # we # ba0 - ba2 a13 - a14 a12/ bc# a10/ ap a0 - a9, a11 notes previous cycle current cycle mode register set mrs h h l l l l ba op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h h x x x x x x x x 7,8,9,12 l h h h v v v v v single bank precharge pre h h l l h l ba v v l v precharge all banks prea h h l l h l v v v h v bank activate act h h l l h h ba row address (ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca 5 write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca 5 write (b l8 , on the fly) wrs 8 h h l h l l ba rfu h l ca 5 write with auto precharge (fixed bl8 or bc4) wra h h l h l l ba rfu v h ca 5 write with auto precharge (bc4, on the fly) wra s4 h h l h l l ba rfu l h ca 5 write with auto precharge (bl8, on the fly) wra s8 h h l h l l ba rfu h h ca 5 read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca 5 read (bc4, on the fly) rds4 h h l h l h ba rfu l l ca 5 read (b l8 , on the fly) rds 8 h h l h l h ba rfu h l ca 5 read with auto precharge (fixed bl8 or bc4) rd a h h l h l h ba rfu v h ca 5 read with auto precharge (bc4, on the fly) rd a s4 h h l h l h ba rfu l h ca 5 read with auto precharge (bl8, on the fly) rd a s8 h h l h l h ba rfu h h ca 5 no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l l h h h v v v v v 6,12 h x x x x x x x x power down exit pd x l h l h h h v v v v v 6,12 h x x x x x x x x zq calibration long zqcl h h l h h l x x x h x zq calibration short zqc s h h l h h l x x x l x
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 95 - note s : 1. all ddr3l sdram commands are defined by states of cs#, ras#, cas#, we# and cke at the rising edge of the clock. the msb of ba, ra and ca are device density and configuration dependant . 2. reset# is low enable command which will be used only for asynchronous reset so must be maintained high during any function . 3. bank addresses (ba) determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register. 4. v means h or l (but a defined logic level) and v means either defined or undefined (like floating) logic level . 5. burst reads or writes cannot be terminated or interrupted and fixed/on - the - f ly bl will be defined by mrs . 6. the power down mode does not perform any refresh operation . 7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh . 8. self refresh exit is asynchronous. 9. v ref (both v ref dq and v ref ca ) must be maintained during self refresh operation. v ref dq supply may be turned off and v ref dq may take any value between v ss and v dd during self refresh operation, provided that v refdq is valid and stable prior to cke going back high and that first write operation or first write lev eling activity may not occur earlier than 512 nck after exit from self refresh . 10. the no operation command should be used in cases when the ddr3l sdram is in an idle or wait state. the purpose of the no operation command (nop) is to prevent the ddr3l sdram f rom register i ng any unwanted commands between operations. a no operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 96 - 9.2 cke truth table notes 1 - 7 apply to the entire cke truth table . for power - down entry and exit parameters see 8 .17 power - down modes on page 6 9 . cke low is allowed only if t mrd and t mod are satisfied. table 1 6 C cke truth table current state 2 cke command (n) 3 ras # , cas # , we # , cs # action (n) 3 notes previous cycle 1 (n - 1) current cycle 1 (n) power down l l x maintain power down 14,15 l h deselect or nop power down exit 11,14 self refresh l l x maintain self refresh 15,16 l h deselect or nop self refresh exit 8,12,16 bank(s) active h l deselect or nop active power down entry 11,13,14 reading h l deselect or nop power down entry 11,13,14,17 writing h l deselect or nop power down entry 11,13,14,17 precharging h l deselect or nop power down entry 11,13,14,17 refreshing h l deselect or nop precharge power down entry 11 all banks idle h l deselect or nop precharge power down entry 11,13,14,1 8 h l refresh self refresh 9,13,18 any other state refer to section 9 .1 command truth table on p age 9 4 for more detail with all command signals 10 note s : 1. cke (n) is the logic state of cke at clock edge n; cke (n - 1) was the state of cke at the previous clock edge . 2. current state is defined as the state of the ddr3l sdram immediately prior to clock edge n . 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n), odt is not included here . 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document . 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh . 6. during any cke transition (registration of cke h - >l or c ke l - >h) the cke level must be maintained until 1nck prior to t cke min being satisfied (at which time cke may transition again) . 7. deselect and nop are defined in the command truth table . 8. on self refresh exit deselect or nop commands must be issued on every c lock edge occurring during the t xs period. read or odt commands may be issued only after t xsdll is satisfied . 9. self refresh mode can only be entered from the all banks idle state . 10. must be a legal command as defined in the command truth table . 11. valid commands for power down entry and exit are nop and deselect only . 12. valid commands for self refresh exit are nop and deselect only . 13. self refresh can not be entered during read or write operations . for a detailed list of restrictions see section 8 .16 self - refresh operation on page 6 7 and see section 8 .17 power - down modes on page 6 9 . 14. the power down does not perform any refresh operations. 15. x means d on't care (including floating around v ref ) in self refresh and power down. it also applies to address pins. 16. v ref (both v refdq and v refca ) must be maintained during self refresh operation. v refdq supply may be turned off and v refdq may take any value between v ss and v dd during self refresh operation, provided that v refdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh . 17. if all banks are closed at the conclusion of the read, write or precharge command, then precharge power down is entered, otherwise active power down is entered. 18. idle state is defined as all banks are closed (t rp , t dal , etc. satisfied), no data bursts are in progress, cke is high, and all timings from previous operations are satisfied (t mrd , t mod , t rfc , t zqinit , t zq oper, t zqcs , etc.) as well as all self refresh exit and power down exit parameters are satisfied (t xs , t xp , t xpdll , etc) .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 97 - 9.3 simplified state diagram this simplified state diagram is intended to provide an overview of the possible state transitions and the commands to control them. in particular, situations involving more than one bank, the enabling or disabling of on - die termination, and some other events are not captured in full detail . figure 8 7 C simplified state diagram table 1 7 C state diagram command definitions abbreviation function abbreviation function abbreviation function act active read rd, rds4, rds8 pde enter power - down pre precharge read a rda, rdas4, rdas8 pdx exit power - down pre a precharge all write wr, wrs4, wrs8 sre self - refresh entry mrs mode register set write a wra, wras4, wras8 srx self - refresh exit ref refresh reset start reset procedure mpr multi - purpose register zqcl zq calibration long zqcs zq calibration short - - note: see command truth table on page 9 4 for more details p o w e r o n r e s e t p r o c e d u r e i n i t i a l i z a t i o n m r s , m p r , w r i t e l e v e l i n g s e l f r e f r e s h z q c a l i b r a t i o n i d l e r e f r e s h i n g a c t i v e p o w e r d o w n a c t i v a t i n g p r e c h a r g e p o w e r d o w n b a n k a c t i v e w r i t i n g w r i t i n g r e a d i n g r e a d i n g p r e c h a r g i n g f r o m a n y s t a t e r e s e t z q c l m r s s r e s r x r e f p d e p d x a c t z q c l , z q c s p d x p d e w r i t e r e a d r e a d a w r i t e a w r i t e a r e a d a p r e , p r e a p r e , p r e a p r e , p r e a w r i t e a r e a d w r i t e w r i t e r e a d c k e _ l c k e _ l c k e _ l a u t o m a t i c s e q u e n c e c o m m a n d s e q u e n c e p o w e r a p p l i e d
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 98 - 10. elec t rical characteristics 10.1 a bsolute m aximum r atings parameter symbol rating unit note s voltage on v dd pin relative to v ss v dd - 0.4 ~ 1.975 v 1, 3 voltage on v ddq pin relative to v ss v ddq - 0.4 ~ 1.975 v 1, 3 voltage on any pin relative to v ss v in , v out - 0.4 ~ 1.975 v 1 s torage temperature t stg - 55 ~ 1 0 0 c 1, 2 note s : 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability . 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51 - 2 standard . 3. v dd and v ddq must be within 300 mv of each other at all times . v refdq and v refca must not greater than 0.6 x v ddq . when v dd and v ddq are less than 500 mv , v refdq and v refca may be equal to or less than 300 mv . 10.2 operating temperature condition parameter symbol rating un it note s commercial operating temperature range ( for - 11/ - 12/ - 15 ) t oper 0 ~ 8 5 c 1, 2 0 ~ 9 5 c 1, 2, 4 industrial operating temperature range (for - 12i/15i) t oper - 4 0 ~ 8 5 c 1, 3 - 4 0 ~ 9 5 c 1, 3, 4 note s : 1. operating temperature t oper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51 - 2 . 2. during operation, the dram case temperatu re must be maintained between 0 to 95c for commercial parts under all specification parameters . 3. during operation, the dram case temperature must be maintained between - 40 to 95c for industrial parts under all specification parameters 4. some application s require operation of the 85 c < t cas e 9 5 c operating temperature. full specifications are provided in this range, but the following additional conditions apply: (a) refresh commands have to be doubled in frequency, therefore reducing the refresh interval t refi to 3.9 s . (b) if self - refresh operation is required in 85 c < t cas e 9 5 c operating temperature range , than it is mandatory to either use the manual self - refresh mode with extended temperature range capability (mr2 a6 = 0 b and mr2 a7 = 1 b ) or enable the auto self - refresh mode (asr) (mr2 a6 = 1 b , mr2 a7 is don't care ). 10.3 dc & ac operating conditions 10.3.1 recommended dc operating conditions sym . parameter m in. typ. max. unit note s v dd supply voltage 1. 283 1. 35 1. 45 v 1 , 2 v ddq supply voltage for output 1. 283 1. 35 1. 45 v 1 , 2 r zq external calibration resistor connected from zq ball to ground 237 . 6 240.0 242 . 4 3 note s : 1. under all conditions v ddq must be less than or equal to v dd . 2. v ddq tracks with v dd . ac parameters are measured with v dd and v dd q tied together . 3. the external calibration resistor rzq can be time - shared among drams in special applications .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 9 9 - 10.4 input and output leakage currents sym bol parameter min . max . unit note s i il input leakage current ( 0v v in v dd ) - 2 2 a 1 i ol output leakage current (output disabled, 0v v out v ddq ) - 5 5 a 2 note s : 1. a ll other ball s not under test = 0 v . 2. all dq , dqs and dqs # are in high - impedance mode . 10.5 interface test conditions figure 8 8 represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measureme nts. it is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference load t o a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics . figure 8 8 C reference load for ac timings and output slew rates the timing reference points are the idealized input and output nodes / terminals on the outside of the packaged sdram device as they would appear in a schematic or an ibis model. the output timing reference voltage level for single ended signals is the cross point with v tt . the output timing reference voltage level for differential signals is the cross point of the true (e.g. dqs ) and the complement (e.g. dqs# ) signal . d q d q s d q s # t i m i n g r e f e r e n c e p o i n t v t t = v d d q / 2 2 5 v d d q d u t c k , c k #
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 100 - 10.6 dc and ac input measurement levels 10.6.1 dc and ac input levels for single - ended co mmand and address signals table 1 8 C single - ended dc and ac input levels for command and address parameter sym bol ddr3l - 1333/1600 ddr3 l - 1 8 66 unit notes min. max. min. max. dc input logic high v ih .ca ( dc90 ) v ref + 0.09 v dd v ref + 0.09 v dd v 1, 5 dc input logic low v i l.ca ( dc90 ) v ss v ref - 0.09 v ss v ref - 0.09 v 1, 6 a c input logic high v ih .ca ( ac 160 ) v ref + 0. 160 note 2 - - v 1, 2, 7 a c input logic low v i l.ca ( ac 160 ) note 2 v ref - 0. 160 - - v 1, 2, 8 a c input logic high v ih .ca ( ac 135 ) v ref + 0. 135 note 2 v ref + 0.1 35 note 2 v 1, 2, 7 a c input logic low v i l.ca ( ac 135 ) note 2 v ref - 0. 135 note 2 v ref - 0.1 35 v 1, 2, 8 a c input logic high v ih .ca ( ac125 ) - - v ref + 0.1 25 note 2 v 1, 2, 7 a c input logic low v i l.ca ( ac125 ) - - note 2 v ref - 0.1 25 v 1, 2, 8 reference voltage for add , cmd inputs v ref ca (dc) 0.49 x v dd 0.51 x v dd 0.49 x v dd 0.51 x v dd v 3, 4 note s : 1. for input only pins except reset#. v ref = v refca(dc) . 2. see section 10 .12 overshoot and undershoot specification s on page 1 20 . 3. the ac peak noise on v ref may not allow v ref to deviate from v ref ca (dc) by more than 1% v dd (for reference: approx. 1 3. 5 mv). 4. for reference: approx. v dd /2 1 3. 5 mv . 5. v ih(dc) is used as a simplified symbol for v ih.ca(dc 9 0) . 6. v il(dc) is used as a simplified symbol for v il.ca(dc 9 0) . 7. vih (ac) is used as a simplified symbol for v ih.ca(ac1 60 ) , v ih.ca(ac1 3 5) and v ih.ca(ac1 2 5) ; v ih.ca(ac1 60 ) value is used when v ref + 0.1 6 v is referenced , v ih.ca(ac1 3 5) value is used when v ref + 0.1 3 5v is referenced and v ih.ca(ac1 2 5) value is used when v ref + 0.1 2 5v is referenced. 8. v il(ac) is used as a simplified symbol for v il.ca(ac1 60 ) , v il.ca(ac1 3 5) and v il.ca(ac1 2 5) ; v il.ca(ac1 60 ) value is used when v ref - 0.1 6 v is referenced , v il.ca(ac135) value is used when v ref - 0.135v is referenced and v il.ca(ac1 2 5) value is used when v ref - 0.1 2 5v is referenced . 10.6.2 dc and ac input levels for single - ended data signals table 1 9 C single - ended dc and ac input levels for dq and dm parameter sym bol ddr3l - 1333/1600 ddr3 l - 1 8 66 unit notes min. max. min. max. dc input logic high v ih .dq ( dc90 ) v ref + 0.09 v dd v ref + 0.09 v dd v 1, 5 dc input logic low v i l.dq ( dc90 ) v ss v ref - 0.09 v ss v ref - 0.09 v 1, 6 a c input logic high v ih .dq ( ac 135 ) v ref + 0. 135 note 2 - - v 1, 2, 7 a c input logic low v i l.dq ( ac 135 ) note 2 v ref - 0. 135 - - v 1, 2, 8 a c input logic high v ih .dq ( ac 130 ) - - v ref + 0. 130 note 2 v 1, 2, 7 a c input logic low v i l.dq ( ac 130 ) - - note 2 v ref - 0. 130 v 1, 2, 8 reference voltage for dq , dm inputs v refdq(dc) 0.49 x v dd 0.51 x v dd 0.49 x v dd 0.51 x v dd v 3, 4 note s : 1. v ref = v ref dq (dc) . 2. see section 10 .12 overshoot and undershoot specification s o n page 1 20 . 3. the ac peak noise on v ref may not allow v ref to deviate from v refdq(dc) by more than 1% v dd (for reference: approx. 1 3. 5 mv). 4. for reference: approx. v dd /2 1 3. 5 mv . 5. v ih(dc) is used as a simplified symbol for v ih.dq(dc 90 ) . 6. v il(dc) is used as a simplified symbol for v il.dq(dc 90 ) . 7. vih (ac) is used as a simplified symbol for v ih. dq (ac1 3 5) ; v ih. dq (ac1 3 5) value is used when v ref + 0.1 3 5v is referenced . 8. v il(ac) is used as a simplified symbol for v il. dq (ac1 3 5) ; v il. dq (ac135) value is used when v ref - 0.135v is referenced .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 101 - the dc - tolerance limits and ac - noise limits for the reference voltages v refca and v refdq are illustrated in figure 8 9 . it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref(dc) is the linear average of v ref (t) over a very long period of time (e.g., 1 sec). this average has to meet the min/max requirements in table 1 8 . furthermore v ref (t) may temporarily deviate from v ref(dc) by no more than 1% v dd . figure 8 9 C illustration of v ref(dc) tolerance and v ref ac - noise limits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) , and v il(dc) are dependent on v r ef . v r ef shall be understood as v r ef (dc) , as defined in figure 8 9 . this clarifies that dc - variations of v r ef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for v r ef (dc) deviations from the optimum position within the data - eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated with v r ef ac - noise. timing and voltage effects due to ac - noise on v r ef up to the specified limit ( 1% of v dd ) are included in dram timings and their associated deratings . v r e f ( d c ) m a x v r e f ( d c ) m i n v d d / 2 v d d v s s v o l t a g e t i m e v r e f ( d c ) v r e f ( t ) v r e f a c - n o i s e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 102 - 10.6.3 differential swing requirements for clock (ck - ck#) and strobe (dqs - dqs#) table 20 C differential dc and ac input level parameter sym. ddr3l - 1333/1600/1866 unit notes min. max. differential input high v ih .diff +0. 18 0 note 3 v 1 differential input low v i l.diff note 3 - 0. 18 0 v 1 differential input high ac v ih . diff ( ac ) 2 x (v ih(ac) - v ref ) note 3 v 2 differential input low ac v i l.diff ( ac ) note 3 2 x (v i l (ac) - v ref ) v 2 note s : 1. used to define a differential signal slew - rate . 2. for ck - ck# use v ih.ca(ac) /v il.ca(ac) of add/cmd and v refca ; for dqs, dqs# us e v ih. dq (ac) /v il. dq (ac) of dqs and v refdq ; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here . 3. these values are not defined; however, the single - ended signals ck, ck#, dqs, dqs# need to be within the respective limits (v ih(dc) max, v il(dc)min ) for single - ended signals as well as the limitations for overshoot and undershoot. refer to section 10 .12 overshoot and undershoot specification s on page 1 20 . figure 90 C definition of differential ac - swing and time above ac - level t dvac t d v a c t d v a c h a l f c y c l e v i h d i f f ( a c ) m i n v i h d i f f m i n 0 v i l d i f f m a x v i l d i f f ( a c ) m a x d i f f e r e n t i a l i n p u t v o l t a g e ( i . e . d q s C d q s # , c k - c k # ) t i m e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 103 - table 2 1 C allowed time before ringback (t dvac ) for ck - ck# and dqs - dqs# slew rate [v/ns] ddr3l - 1333/1600 ddr3l - 1866 t dvac [p s ] @ |v ih/l diff ( ac ) | = 3 2 0mv t dvac [p s ] @ |v ih/l diff ( ac ) | = 27 0mv t dvac [p s ] @ |v ih/l diff ( ac ) | = 27 0mv t dvac [p s ] @ |v ih/l diff ( ac ) | = 25 0mv t dvac [p s ] @ |v ih/l diff ( ac ) | = 26 0mv m in . m ax . m in . m ax . m in . m ax . m in . m ax . m in . m ax . > 4.0 189 - 201 - 1 63 - 1 68 1 76 - 4.0 189 - 201 - 1 63 - 1 68 1 76 - 3.0 162 - 179 - 1 40 - 1 47 1 54 - 2.0 109 - 134 - 95 - 105 111 - 1.8 91 - 119 - 80 - 91 97 - 1.6 69 - 100 - 62 - 74 78 - 1.4 40 - 76 - 37 - 52 56 - 1.2 note - 44 - 5 - 22 24 - 1.0 note - note - note - note note - < 1.0 note - note note - note note - note: rising input signal shall become equal to or greater than v ih( ac ) level and falling input signal shall become equal to or less than v il( ac ) level. 10.6.4 single - ended requirements for differential signals each individual component of a different ial signal ( ck, dqs, ck#, dqs# ) has also to comply with certain requirements for single - ended signals. ck and ck# have t o approximately reach v seh min / v sel max (approximately equal to the ac - levels (v ih .ca (ac) / v il .ca (ac) ) for add/cmd signals) in every half - cycle. dqs, dqs # have to reach v seh min / v sel max (approxima tely the ac - levels (v ih .dq (ac) / v il .dq (ac) ) for dq signals) in every half - cycle preceding and following a valid transition. note that the applicable ac - levels for add/cmd and dqs might be differ ent per speed - bin etc. e.g., if v ih .ca (ac 1 35 ) / v i l.ca (ac 1 35 ) is used for add/cmd signals, then the se ac - levels apply also for the single - ended signals ck and ck# . table 2 2 C single - ended levels for ck, dqs, ck#, dqs# parameter sym bol ddr3l - 1333/1600/1866 unit notes min. max. single - ended high level for strobes v seh (v dd /2) + 0.1 60 note 3 v 1, 2 single - ended high level for ck, ck# (v dd /2) + 0.1 60 note 3 v 1, 2 single - ended low level for strobes v sel note 3 (v dd /2) - 0.1 60 v 1, 2 single - ended low level for ck, ck# note 3 (v dd /2) - 0.1 60 v 1, 2 note s : 1. for ck, ck# use v ih.ca(ac) / v il. . ca(ac) of add/cmd; for strobes ( dqs, dqs# ) use v ih. dq (ac) / v il. dq (ac) of dqs . 2. v ih. dq (ac) / v il. dq (ac) for dqs is based on v refdq ; v ih.ca(ac) / v il . ca(ac) for add/cmd is based on v refca ; if a reduced ac - high or ac - low level is used for a signal group, then the reduced level applies also here . 3. these values are not defined; however, the single - ended signals k, ck# , dqs, dqs# need to be within the respective limits (v ih(dc) max, v il(dc)min ) for single - ended signals as well as the limitations for overshoot and undershoot. ref er to section 10 .12 overshoot and undershoot specification s on page 1 20 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 104 - figure 9 1 C single - ended requirement for differential signals note that, while add/cmd and dq signal requirements are with respect to v ref , the single - ended components of differential signals have a requirement with respect to v dd / 2; this is nominally the same. the transition of single - ended signals through the ac - levels is used to measure setup time. for single - ended components of differential si gnals the requirement to reach v sel max, v seh min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. 10.6.5 differential input cross point voltage to guarantee tight setup and hold times as well as output skew para meters wi th respect to clock and strobe, each cross point voltage of differential input signals (ck, ck# and dqs, dqs#) must meet the requirements in table 2 3 . the differential input cross point voltage v ix is measured from the actual cross point of true and complement signals to the midlevel between of v dd and v ss . figure 9 2 C v ix definition v d d o r v d d q v s e h m i n v d d / 2 o r v d d q / 2 v s e l m a x v s s o r v s s q v s e h v s e l c k o r d q s t i m e v i x v i x v i x v d d / 2 c k # , d q s # c k , d q s v d d v s s v s e h v s e l
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 105 - table 2 3 C cross point voltage for differential input signals (ck, dqs) parameter sym bol ddr3l - 1333/1600/1866 unit notes min. max. differential input cross point voltage v ix(ck) - 150 150 mv 1 relative to v dd /2 for ck, ck# differential input cross point voltage v ix(dqs) - 150 150 mv relative to v dd /2 for dqs, dqs# note: 1. the relation between v ix min/max and v sel /v seh should satisfy following. (v dd /2) + v ix (min) - vsel 25mv v seh - ((v dd /2) + v ix (max)) 25mv 10.6.6 slew rate definitions for single - ended input signals see section 10 .16. 4 address / command setup, hold and derating on page 1 4 8 for sin gle - ended slew rate definitions for address and command signals . see section 10 .16. 5 data setup, hold and slew rate derating on page 1 55 for single - ended slew rate definitions for data signals . 10.6.7 slew rate definitions for differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are d efined and measured as shown i n table 2 4 and figure 9 3 . table 2 4 C differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck - ck# and dqs - dqs#) v il .diff max v i h.diff m in [v i h.diff m in - v il .diff max ] / t r. diff differential input slew rate for falling edge (ck - ck# and dqs - dqs#) v i h.diff m in v il .diff max [v i h.diff m in - v il .diff max ] / t f. diff note: the differential signal (i.e., ck - ck# and dqs - dqs#) must be linear between these thresholds figure 9 3 C differential input slew rate definition for dqs, dqs# and ck, ck# v i h . d i f f m i n 0 v i l . d i f f m a x t f . d i f f t r . d i f f d i f f e r e n t i a l i n p u t v o l t a g e ( d q s - d q s # ; c k - c k # )
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 106 - 10.7 dc and ac output measurement levels table 2 5 C single - ended dc and ac output levels parameter sym bol value unit note s dc output high measurement level (for iv curve linearity) v oh(dc) 0.8 x v ddq v dc output mid measurement level (for iv curve linearity) v o m (dc) 0. 5 x v ddq v dc output low measurement level (for iv curve linearity) v o l (dc) 0. 2 x v ddq v ac output high measurement level ( for output slew rate ) v oh( a c) v tt + 0.1 x v ddq v 1 ac output low measurement level ( for output slew rate ) v o l ( a c) v tt - 0.1 x v ddq v 1 note: 1. the swing of 0.1 v ddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 34 and an effective test load of 25 to v tt = v ddq /2 . table 2 6 C differential dc and ac output levels parameter sym bol value unit note s min. m ax . ac differential output high measurement level ( for output slew rate ) v oh.diff(ac) + 0. 2 x v ddq v 1 ac differential output low measurement level ( for output slew rate ) v o l .diff(ac) - 0. 2 x v ddq v 1 note: 1. the swing of 0. 2 v ddq is based on approximately 50% of the static single - ended output high or low swing with a driver impedance of 34 and an effective test load of 25 to v tt = v ddq /2 at each of the differential outputs . 10.7.1 output slew rate definition and requirements the slew rate definition depends if the signal is single - ended or differential. for the relevant ac output reference levels see above table 2 5 and table 2 6 . table 2 7 C output slew rate parameter symbol ddr3l - 1333/1600/1866 unit notes min. max. single - ended output slew rate srqse 1.75 5 1) v/ns 1, 2, 3 differential output slew rate srq diff 3.5 12 v/ns 1, 2, 3 note s : 1. in two cases, a maximum slew rate of 6 v/ns applies for a single dq signal within a byte lane. - case 1 is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i.e they stay at either high or low). - case 2 is de fined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are switching into the opposite direction (i.e. from low to high or hi gh to low respectively). for the remaining dq signal switching into the opposite direction, the regular maximum limit of 5 v/ns applies. 2. background for symbol nomenclature: sr: slew rate; q: query output (like in dq, which stands for data - in, query - output) ; se: single - ended signals ; diff: differential signals . 3. for r on = rzq/7 settings only .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 107 - 10.7.1.1 single ended output slew rate with the reference load for timing measurements, output slew rate for fall ing and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals as shown in table 2 8 and figure 9 4 . table 2 8 C single - ended output slew rate definition description measured defined by from to single - ended output slew rate for rising edge v ol(ac) v o h (ac) [v oh(ac) - v ol(ac) ] / trse single - ended output slew rate for falling edge v o h (ac) v ol(ac) [v oh(ac) - v ol(ac) ] / tfse note: output slew rate is verified by design and characterization, and may not be subject to production test. figure 9 4 C single - ended output slew rate definition v o h ( a c ) v t t v o l ( a c ) t f s e t r s e s i n g l e - e n d e d o u t p u t v o l t a g e ( i . e . d q )
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 108 - 10.7.1.2 differential output slew rate with the reference load for timing measurements, output slew rate for fall ing and rising edges is defined and measured between v ol . diff ac) and v oh . diff (ac) for differential signals as shown in table 2 9 and figure 9 5 . table 2 9 C differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v o l .diff(ac) v oh.diff(ac) [v oh.diff(ac) - v o l .diff(ac) ] / tr diff differential output slew rate for falling edge v oh.diff(ac) v o l .diff(ac) [v 0h.diff(ac) - v o l .diff(ac) ] / tf diff note: output slew rate is verified by design and characterization, and may not be subject to production test . figure 9 5 C differential output slew rate definition v o h . d i f f ( a c ) 0 v o l . d i f f ( a c ) t f d i f f t r d i f f d i f f e r e n t i a l o u t u t v o l t a g e ( d q s - d q s # )
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 109 - 10.8 34 o hm output driver dc electrical characteristics a functional representation of the output buffer is shown in figure 96 . output driver impedance ron is selected by bits d . i . c a1 and a5 in the mr1 register. four different values can be selected via mr1 settings : ron 34 = r zq / 7 (nominal 34.3 10% with nominal r zq = 240 ) ron 40 = r zq / 6 (nominal 40 . 0 10% with nominal r zq = 240 ) the individual pull - up and pull - down resistors ( ron pu and ron pd ) are defined as follows : ron pu = under the condition that ron pd is turned off ron pd = under the condition that ron p u is turned off figure 9 6 C output driver: definition of voltages and currents out out ddq i v - v out out i v v s s q d q v d d q v o u t o u t p u t d r i v e r i p d r o n p d r o n p u i p u t o o t h e r c i r c u i t r y l i k e r c v , . . . i o u t c h i p i n d r i v e m o d e
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 110 - table 30 C output driver dc electrical characte ristics, assuming rzq = 240 ; entire operating temperature range; after proper zq calibration r on nom resistor v out min. nom. max. unit notes 34 ron 34 pd v oldc = 0.2 v ddq 0.6 1.0 1.1 5 rzq / 7 1, 2, 3 v o m dc = 0. 5 v ddq 0.9 1.0 1.1 5 rzq / 7 1, 2, 3 v o h dc = 0. 8 v ddq 0.9 1.0 1.4 5 rzq / 7 1, 2, 3 ron 34 p u v oldc = 0.2 v ddq 0.9 1.0 1.4 5 rzq / 7 1, 2, 3 v o m dc = 0. 5 v ddq 0.9 1.0 1.1 5 rzq / 7 1, 2, 3 v o h dc = 0. 8 v ddq 0.6 1.0 1.1 5 rzq / 7 1, 2, 3 40 ron 40 pd v oldc = 0.2 v ddq 0.6 1.0 1.1 5 rzq / 6 1, 2, 3 v o m dc = 0. 5 v ddq 0.9 1.0 1.1 5 rzq / 6 1, 2, 3 v o h dc = 0. 8 v ddq 0.9 1.0 1.4 5 rzq / 6 1, 2, 3 ron 40 p u v oldc = 0.2 v ddq 0.9 1.0 1.4 5 rzq / 6 1, 2, 3 v o m dc = 0. 5 v ddq 0.9 1.0 1.1 5 rzq / 6 1, 2, 3 v o h dc = 0. 8 v ddq 0.6 1.0 1.1 5 rzq / 6 1, 2, 3 mismatch between pull - up and pull - down, mm pupd v o m dc = 0. 5 v ddq - 10 +10 % 1, 2, 4 note s : 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss . 3. pull - down and pull - up output driver impedances are recommended to be calibrated at 0.5 v ddq . other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 v ddq and 0.8 v ddq . 4. measurement definition for mismat ch between pull - up and pull - down, mm pupd : measure ron pu and ron pd , both at 0.5 * v ddq : mm pu pd = x 100% nom pd pu ron ron - ron
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 111 - 10.8.1 output driver temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table 3 1 and table 3 2 . t = t - t(@calibration); v= v ddq - v ddq (@calibration); v dd = v ddq note: dr on dt and dr on dv are not subject to production test but are verified by design and characterization . table 3 1 C output driver sensitivity definition min. max. unit ron pu @ v oh dc 0.6 - dr on dth*| t| - dr on dvh*| v| 1.1 + dr on dth*| t| + dr on dvh*| v| rzq / 7 ron@ v om dc 0. 9 - dr on dt m *| t| - dr on dv m *| v| 1.1 + dr on dt m *| t| + dr on dv m *| v| rzq / 7 ron pd @ v ol dc 0.6 - dr on dt l *| t| - dr on dv l *| v| 1.1 + dr on dt l *| t| + dr on dv l *| v| rzq / 7 table 3 2 C output driver voltage and temperature sensitivity speed bin ddr3l - 1333 ddr3l - 1600/1866 unit min. max. min. max. dr on dt m 0 1.5 0 1.5 %/c dr on d vm 0 0.15 0 0.13 %/mv dr on dt l 0 1.5 0 1.5 %/c dr on d vl 0 0.15 0 0.13 %/mv dr on dt h 0 1.5 0 1.5 %/c dr on d vh 0 0.15 0 0.13 %/mv note: these parameters may not be subject to production test. they are verified by design and characterization.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 112 - 10.9 on - die termination (odt) levels and characteristics 10.9.1 odt levels and i - v characteristics on - die termination effective resistance r tt is defined by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm and dqs/dqs# pins. a functional representation of the on - die termination is shown in figure 9 7 . the individual pull - up and pull - down resistors ( r tt pu and r tt pd ) are defined as follows: r tt pu = under the condition that r tt pd is turned off r tt pd = under the condition that r tt p u is turned off figure 9 7 C on - die termination: definition of voltages and currents out out ddq i v v - out out i v v s s q d q v d d q v o u t o d t i p d r t t p d r t t p u i p u t o o t h e r c i r c u i t r y l i k e r c v , . . . i o u t c h i p i n t e r m i n a t i o n m o d e i o u t = i p d - i p u
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 113 - 10.9.2 odt dc electrical characteristics an overview about the specification requirements for r tt and v m is provided in table 3 3 . table 3 3 C odt dc impedance and mid - level requirements mr1 a9, a6, a2 r tt resistor v out min. nom. max. unit notes 0, 1, 0 120 r tt 120 0.9 1.0 1.6 5 r zq /2 1, 2, 3, 4 0, 0, 1 6 0 r tt 6 0 0.9 1.0 1.6 5 r zq / 4 1, 2, 3, 4 0, 1, 1 4 0 r tt 4 0 v il(ac) to v ih(ac) 0.9 1.0 1.6 5 r zq / 6 1, 2, 3, 4 1, 0, 1 3 0 r tt 3 0 0.9 1.0 1.6 5 r zq / 8 1, 2, 3, 4 1, 0, 0 2 0 r tt 2 0 0.9 1.0 1.6 5 r zq / 1 2 1, 2, 3, 4 deviation of v m with respect to v ddq /2, v m - 5 +5 % 1, 2, 3, 4, 5 note s : 1. with rzq = 240 . 2. the tolerance limits are specified after calibration with stable voltage a nd temperature. for the behavio r of the tolerance limits if temperature or voltage changes after calibration, see the following section odt temperature and voltage sensitivity . 3. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss . 4. measurement definition for r tt : apply v ih(ac) to pin under test and measure current i( v ih(ac) ), then apply v i l (ac) to pin under test and measure current i( v i l (ac) ) respectively. calculate r tt as follows: r tt = [ v ih(ac) - v il(ac) ] / [ i ( v ih(ac) ) - i ( v il(ac) )] 5. measurement d efinition for v m and v m : measure voltage (v m ) at test pin (midpoint) with no load . calculate v m as follows: v m = (2 v m / v ddq - 1) 100% . 10.9.3 odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table 3 4 and table 3 5 . the following definitions are used: t = t - t ( @calibration ) ; v = v ddq - v ddq ( @calibration ) ; v dd = v ddq table 3 4 C odt sensitivity definition sym bol min. max. unit r tt 0.9 - dr tt dt |t| - dr tt dv |v| 1.6 + dr tt dt |t| + dr tt dv |v| rzq/2,4,6,8,12 table 3 5 C odt voltage and temperature sensitivity sym bol min. max. unit dr tt dt 0 1.5 %/c dr tt d v 0 0.15 %/mv note: these parameters may not be subject to production test. they are verified by design and characterization
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 114 - 10.9.4 design guide lines for r tt pu and r tt pd table 3 6 provides an overview of the odt dc electrical pull - up and pull - down characteristics. the values are not specification requirements, but can be used as design guide lines . table 3 6 C odt dc electrical pull - down and pull - up characteristics, assuming r zq = 240 1% entire operating temperature range; after proper zq calibration mr1 a9, a6, a2 r tt resistor v out min. nom. max. unit notes 0, 1, 0 120 , r tt 120pd240 , v oldc = 0.2 v ddq 0.6 1.0 1.15 r zq /tisf pupd 1, 2, 3, 4, 5 0, 0, 1 60 , r tt 60pd120 , v omdc = 0.5 v ddq 0.9 1.0 1.15 r zq /tisf pupd 1, 2, 3, 4, 5 0, 1, 1 40 , r tt 40pd80 , v ohdc = 0.8 v ddq 0.9 1.0 1.45 r zq /tisf pupd 1, 2, 3, 4, 5 1, 0, 1 30 , r tt 30pd60 , 1, 0, 0 20 r tt 20pd40 r tt 120p u 240 , v oldc = 0.2 v ddq 0.9 1.0 1.45 r zq /tisf pupd 1, 2, 3, 4, 5 r tt 60p u 120 , v omdc = 0.5 v ddq 0.9 1.0 1.15 r zq /tisf pupd 1, 2, 3, 4, 5 r tt 40p u 80 , v ohdc = 0.8 v ddq 0.6 1.0 1.15 r zq /tisf pupd 1, 2, 3, 4, 5 r tt 30p u 60 , r tt 20p u 40 note s : 1. tisf pupd : termination impedance scaling factor for pull - up and pull - down path: tisf pupd = 1 for r tt 120pu/pd240 tisf pupd = 2 for r tt 60pu/pd120 tisf pupd = 3 for r tt 40pu/pd 80 tisf pupd = 4 for r tt 30pu/pd60 tisf pupd = 6 for r tt 20pu/pd40 2. the tolerance limits are specified after calibration with stable voltage a nd temperature. for the behavio r of the tolerance limits if temperature or voltage changes after calibration, see the above section odt temperature and voltage sensitivity . 3. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss . 4. pull - down and pull - up odt resistors are recommended to be calibrated at 0.5 v ddq . other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 v ddq and 0.8 v ddq . 5. not a specification requirement, but a design guide line.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 115 - 10.10 odt timing definitions 10.10.1 test load for odt timings different than for timing measurements, the reference load for odt timings is defined in figure 9 8 . figure 9 8 C odt timing reference load 10.10.2 odt timing definitions definitions for t aon , t aonpd , t aof , t aofpd and t adc are provided in table 3 7 and subsequent figures. measurement reference settings are provided in table 3 7 . table 3 7 C odt timing definitions s ymbol begin point definition end point definition figure t aon rising edge of ck - ck# defined by the end point of odtlon extrapolated point at v ssq figure 9 9 t aonpd rising edge of ck - ck# with odt being first registered high extrapolated point at v ssq figure 100 t aof rising edge of ck - ck#defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure 101 t aofpd rising edge of ck - ck# with odt being first registered low end point: extrapolated point at vrtt_nom figure 102 t adc rising edge of ck - ck# defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure 10 3 table 3 8 C reference settings for odt timing measurements measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw 2 [v] t aon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t aofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 t adc r zq / 12 rzq/ 2 0.20 0.25 d q , d m d q s , d q s # t i m i n g r e f e r e n c e p o i n t v t t = v s s q r t t = 2 5 v d d q d u t c k , c k # v s s q t d q s , t d q s #
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 116 - figure 9 9 C definition of t aon igure 100 C definition of t aon pd c k c k # t a o n v s s q v s w 2 v s w 1 t s w 1 t s w 2 e n d p o i n t : e x t r a p o l a t e d p o i n t a t v s s q d q , d m d q s , d q s # t d q s , t d q s # b e g i n p o i n t : r i s i n g e d g e o f c k C c k # d e f i n e d b y t h e e n d p o i n t o f o d t l o n v t t v s s q c k c k # t a o n p d v s s q v s w 2 v s w 1 t s w 1 t s w 2 e n d p o i n t : e x t r a p o l a t e d p o i n t a t v s s q d q , d m d q s , d q s # t d q s , t d q s # b e g i n p o i n t : r i s i n g e d g e o f c k - c k # w i t h o d t b e i n g f i r s t r e g i s t e r e d h i g h v t t v s s q
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 117 - figure 10 1 C definition of t ao f figure 10 2 C definition of t ao f pd c k c k # t a o f v s w 2 v s w 1 t s w 1 t s w 2 e n d p o i n t : e x t r a p o l a t e d p o i n t a t v r t t _ n o m d q , d m d q s , d q s # t d q s , t d q s # b e g i n p o i n t : r i s i n g e d g e o f c k - c k # d e f i n e d b y t h e e n d p o i n t o f o d t l o f f v t t v s s q v r t t _ n o m c k c k # t a o f p d v s w 2 v s w 1 t s w 1 t s w 2 e n d p o i n t : e x t r a p o l a t e d p o i n t a t v r t t _ n o m d q , d m d q s , d q s # t d q s , t d q s # b e g i n p o i n t : r i s i n g e d g e o f c k C c k # w i t h o d t b e i n g f i r s t r e g i s t e r e d l o w v t t v s s q v r t t _ n o m
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 118 - figure 10 3 C definition of t a dc c k c k # t a d c v s w 2 v s w 1 t s w 1 t s w 2 1 e n d p o i n t : e x t r a p o l a t e d p o i n t a t v r t t _ n o m d q , d m d q s , d q s # t d q s , t d q s # b e g i n p o i n t : r i s i n g e d g e o f c k C c k # d e f i n e d b y t h e e n d p o i n t o f o d t l c n w v r t t _ n o m t a d c t s w 1 t s w 2 e n d p o i n t : e x t r a p o l a t e d p o i n t a t v r t t _ w r b e g i n p o i n t : r i s i n g e d g e o f c k C c k # d e f i n e d b y t h e e n d p o i n t o f o d t l c w n 4 o r o d t l c w n 8 v t t v r t t _ n o m v r t t _ w r v s s q
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 119 - 10.11 input/output capacitance parameter symbol ddr3 l - 1 333 ddr3 l - 1 600 ddr3 l - 1 866 unit notes min. max. min. max. min. max. input/output capacitance (dq, dm, dqs, dqs#, t dqs, t dqs#) c io 1.4 2. 3 1.4 2. 2 1.4 2. 1 pf 1,2, 3 input capacitance ( ck and ck# ) c ck 0.8 1.4 0.8 1.4 0.8 1.3 pf 2, 3 delta of i nput c apacitance ( ck and ck# ) c dck 0 0.15 0 0.15 0 0.15 pf 2,3, 4 delta of input/ o utput capacitance ( dqs and dqs# ) c ddqs 0 0.15 0 0.15 0 0.15 pf 2,3, 5 input capacitance (ctrl, add, cmd input - only pins) c i 0.75 1.3 0.75 1. 2 0.75 1.2 pf 2, 3,6 delta of input capacitance (all ctrl input - only pins) c di_ctrl - 0.4 0.2 - 0.4 0.2 - 0.4 0.2 pf 2,3,7, 8 delta of input capacitance (all add/cmd input - only pins) c di_add_cmd - 0.4 0.4 - 0.4 0.4 - 0.4 0.4 pf 2,3,9, 10 delta of input/output capacitance (dq, dm, dqs, dqs#, t dqs, t dqs#) c dio - 0.5 0.3 - 0.5 0.3 - 0.5 0.3 pf 2,3, 11 input/output capacitance of zq signal c zq ? 3 ? 3 ? 3 pf 2,3, 12 note s : 1. although the dm, tdqs and tdqs# pin s have different functions, the loading matches dq and dqs . 2. this parameter is not subject to production test. it is verified by design and characterization. the c apacitance is measured according to jep147 (procedure for measuring input capacitance using a vector network analyzer (vna) wi th v dd , v ddq , v ss , v ssq appl ied and all other pin s floating (except the ball under test, cke, reset# and odt as necessary). v dd =v ddq = 1. 3 5v , v bias =v dd /2 and on - die termination off . 3. this parameter applies to monolithic devices only; stacked/dual - die devices are not covered here . 4. absolute value of c ck - c ck # . 5. absolute value of c io (dqs) - c io (dqs#) . 6. c i applies to odt, cs#, cke , a0 - a1 4 , ba0 - ba2, ras#, cas#, we# . 7. c di_ctrl applies to odt, cs# and cke . 8. c di_ctrl =c i (ctrl) - 0.5*(c i (clk)+c i (clk#)) . 9. c di_add_cmd applies to a0 - a1 4 , ba0 - ba2, ras#, cas# and we# . 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk#)) . 11. c dio =c io (dq,dm) - 0.5*(c io (dqs) +c io (dqs#) ) . 12. maximum external load capacitance on zq signal: 5 pf .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 120 - 10.12 overshoot and undershoot specification s 10.12.1 ac overshoot /undershoot specification for address and control pins: applies to a0 - a1 4 , ba0 - ba 2 , cs#, ras#, cas#, we#, cke, odt parameter ddr3 l - 1 333 ddr3 l - 1 600 ddr3 l - 1 866 unit maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 v maximum overshoot area above v dd 0.4 0.33 0.28 v - ns maximum undershoot area below v ss 0.4 0.33 0.28 v - ns 10.12.2 ac overshoot /undershoot specification for clock, data, strobe and mask pins: applies to ck, ck#, dq, dqs, dqs#, dm parameter ddr3 l - 1 333 ddr3 l - 1 600 ddr3 l - 1 866 unit maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 v maximum overshoot area above v dd q 0.15 0.13 0.11 v - ns maximum undershoot area below v ss q 0.15 0.13 0.11 v - ns figure 10 4 C ac o vershoot and u ndershoot d efinition maximum amplitude maximum amplitude overshoot area undershoot area v dd / v ddq volts ( v ) time ( ns ) v ss / v ssq
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 121 - 10.13 i dd and i ddq specification parameters and test conditions 10.13.1 i dd and i ddq measurement conditions in this section , i dd and i ddq measurement conditions such as test load and patterns are defined. figure 10 5 shows the setup and test load for i dd and i ddq measurements. ? i dd currents (such as i dd0 , i dd1 , i dd2n , i dd2nt , i dd2p0 , i dd2p1 , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , i dd5b , i dd6 , i dd6et and i dd7 ) are measured as time - averaged currents with all v dd balls of the ddr3l sdram under test tied together. any i ddq current is not included in i dd currents. ? i ddq currents (such as i ddq2nt and i ddq4r ) are measured as time - averaged currents with all v ddq balls of the ddr3l sdram under test tied together. any i dd current is not included in i ddq currents. attention: i ddq values cannot be directly used to calculate io power of the ddr3l sdram. they can be used to support correlation of simulated io power to actual io power as outlined in figure 10 6 . in dram module application, iddq cannot be measured separately since v dd and v ddq are using one merged - power layer in module pcb. for idd and i ddq measurements, the following definitions apply: ? 0 and low is defined as v in v ilac (max) . ? 1 and high is defined as v in v ihac (min) . ? mid - level is defined as inputs are v ref = v dd / 2 . ? timings used for i dd and i ddq measurement - loop patterns are provided in table 3 9 . ? basic i dd and i ddq measurement conditions are described in table 40 . ? detailed i dd and i ddq measurement - loop patterns are described in table 4 1 through table 4 8 . ? i dd measurements are done after properly i nitializing the ddr3l sdram. this includes but is not limited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); r tt _nom = rzq/6 (40 ohm in mr1); r tt _w r = rzq/2 (120 ohm in mr2); ? attention: the i dd and i ddq measurement - loop patterns need to be executed at least one time before actual i dd or i ddq measurement is started. ? define d = {cs#, ras#, cas#, we# } := {high, low, low, low} ? define d# = {cs#, ras#, cas#, we# } := {high, high, high, high} table 3 9 C timing s used for idd and iddq measurement - loop patterns s peed bin ddr3 l - 1333 ddr3 l - 1600 ddr3 l - 1 866 u nit cl - n rcd - n rp 9 - 9 - 9 11 - 11 - 11 13 - 13 - 13 part number extension - 15/15i - 12/12i - 11 t ck 1.5 1.25 1.07 ns cl 9 1 1 13 nck nrcd 9 1 1 13 nck nrc 3 3 39 45 nck nras 2 4 28 32 nck nrp 9 1 1 13 nck nfaw 20 24 26 nck nrrd 4 5 5 nck nrfc 2 gb 107 12 8 1 50 nck
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 122 - figure 10 5 C measurement setup and test load for i dd and i ddq (optional) measurements figure 10 6 C correlation from simulated channel io power to actual channel io power supported by i ddq measurement r e s e t # c k / c k # c k e c s # r a s # , c a s # , w e # a , b a o d t z q v s s v s s q d q s , d q s # d q , d m t d q s , t d q s # d d r 3 s d r a m v d d v d d q i d d i d d q ( o p t i o n a l ) v d d q / 2 r t t = 2 5 n o t e : d i m m l e v e l o u t p u t t e s t l o a d c o n d i t i o n m a y b e d i f f e r e n t f r o m a b o v e . a p p l i c a t i o n s p e c i f i c m e m o r y c h a n n e l e n v i r o n m e n t c h a n n e l i o p o w e r s i m u l a t i o n c o r r e l a t i o n c o r r e l a t i o n c h a n n e l i o p o w e r n u m b e r i d d q t e s t l o a d i d d q s i m u l a t i o n i d d q m e a s u r e m e n t
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 123 - table 40 C basic idd and i ddq measurement conditions sym. description i dd0 operating one bank active - precharge current cke: high; external clock: on; t ck , nrc, nras, cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: high between act and pre; command, address, bank address inputs: partially toggling according to table 4 1 ; data io: mid - level; dm: stable at 0; bank activity: cycling with one bank active at a ti me: 0,0,1,1,2,2,... (see table 4 1 ); output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 1 i dd1 operating one bank active - read - precharge current cke: high; external clock: on; t ck , nrc, nras, nrcd, cl: see table 3 9 ; bl: 8 (1,6) ; al: 0; cs#: high between act, rd and pre; command, address, bank address inputs, data io: partially toggling according to table 4 2 ; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 4 2 ); output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 2 i dd2n precharge standby current cke: high; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: partially toggling according to table 4 3 ; data io: mid - level; dm: stable at 0; bank activity: all banks closed; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 3 i dd2nt precharge standby odt current cke: high; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: partially toggling according to table 4 4 ; data io: mid - level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers (2) ; odt signal: toggling according to table 4 4 ; pattern details: see table 4 4 i ddq2nt precharge standby odt i ddq current same definition like for i dd2nt , however measuring i ddq current instead of i dd current i dd2p0 precharge power - down current slow exit cke: low; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm: stable at 0; bank activity: all banks closed; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pecharge power down mode: slow exit (3) i dd2p1 precharge power - down current fast exit cke: low; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm: stable at 0; bank activity: all banks closed; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pecharge power down mode: fast exit (3) i dd2q precharge quiet standby current cke: high; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm: stable at 0; bank activity: all banks closed; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: partially toggling according to table 4 2 ; data io: mid - level; dm: stable at 0; bank activity: all banks open; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 3 i dd3p active power - down current cke: low; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: stable at 1; command, address, bank address inputs: stable at 0; data io: mid - level; dm: stable at 0; bank activity: all banks open; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 124 - basic idd and iddq measurement conditions , continued sym. description i dd4r operating burst read current cke: high; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1,6) ; al: 0; cs#: high between rd; command, address, bank address inputs: partially toggling according to table 4 5 ; data io: seamless read data burst with different data between one burst and the next one according to table 4 5 ; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,... (see table 4 4 ); output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 5 i ddq4r operating burst read i ddq current same definition like for i dd 4r , however measuring i ddq current instead of i dd current i dd4w operating burst write current cke: high; external clock: on; t ck , cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: high between wr; command, address, bank address inputs: partially toggling according to table 4 6 ; data io: seamless write data burst with different data between one burst and the next one according to table 4 6 ; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,... (see table 4 6 ); output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at high; pattern details: see table 4 6 i dd5b burst refresh current cke: high; external clock: on; t ck , cl, nrfc: see table 3 9 ; bl: 8 (1) ; al: 0; cs#: high between ref; command, address, bank address inputs: partially toggling according to table 4 7 ; data io: mid - level; dm: stable at 0; bank activity: ref command every nrfc (see table 4 7 ); output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 7 i dd6 self refresh current: normal temperature range t case : 0 - 85c; auto self - refresh (asr): disabled (4) ; self - refresh temperature range (srt): normal (5) ; cke: low; external clock: off; ck and ck#: low; cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#, command, address, bank address, data io: mid - level; dm: stable at 0; bank activity: self - refresh operation; output buffer and r tt : enabled in mode registers (2) ; odt signal: mid - level i dd6et self - refresh current: extended temperature range t case : 0 - 95c; auto self - refresh (asr): disabled (4) ; self - refresh temperature range (srt): extended (5) ; cke: low; external clock: off; ck and ck#: low; cl: see table 3 9 ; bl: 8 (1) ; al: 0; cs#, command, address, bank address, data io: mid - level; dm: stable at 0; bank activity: extended temperature self - refresh operation; output buffer and r tt : enabled in mode registers (2) ; odt signal: mid - level i dd7 operating bank interleave read current cke: high; external clock: on; t ck , nrc, nras, nrcd, nrrd, nfaw, cl: see table 3 9 ; bl: 8 (1,6) ; al: cl - 1; cs#: high between act and rda; command, address, bank address inputs: partially toggling according to table 4 8 ; data io: read data bursts with different data between one burst and the next one according to table 4 8 ; dm: stable at 0; bank a ctivity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see table 4 8 ; output buffer and r tt : enabled in mode registers (2) ; odt signal: stable at 0; pattern details: see table 4 8 i dd8 reset # low current reset # : l ow ; external clock: off; ck and ck#: l ow ; cke: floating; cs#, command, address, bank address, data io: floating; odt signal: floating reset # low current reading is valid once power is stable and reset has been l ow for at least 1ms note s : 1. burst length: bl8 fix ed by mrs: set mr0 a[1,0]=00 b . 2. output buffer enable: set mr1 a[12] = 0 b ; set mr1 a[5,1] = 01 b ; r tt _nom enable: set mr1 a[9,6,2] = 011 b ; r tt _w r enable: set mr2 a[10,9] = 10 b . 3. pecharge power down mode: set mr0 a12=0 b for slow exit or mr0 a12=1 b for fast exit. 4. auto self - refresh (asr): set mr2 a6 = 0 b to disable or 1 b to enable feature. 5. self - refresh temperature range (srt): set mr2 a7=0 b for normal or 1 b for extended temperature range. 6. read burst type: nibble sequential, set mr0 a[3] = 0 b.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 125 - table 4 1 C i dd0 measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 act 0 0 1 1 0 0 0 0 0 0 0 - 1, 2 d, d 1 0 0 0 0 0 0 0 0 0 0 - 3, 4 d#, d# 1 1 1 1 0 0 0 0 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 0 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 0 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 0 0 0 f 0 - 1*nrc+ 3 , 4 d#, d# 1 1 1 1 0 0 0 0 0 f 0 - ... repeat pattern nrc + 1,...,4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 0 0 0 f 0 - ... repeat pattern nrc + 1,...,4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub - loop 0, use ba[2:0] = 1 instead 2 4 *nrc repeat sub - loop 0, use ba[2:0] = 2 instead 3 6 *nrc repeat sub - loop 0, use ba[2:0] = 3 instead 4 8 *nrc repeat sub - loop 0, use ba[2:0] = 4 instead 5 10 *nrc repeat sub - loop 0, use ba[2:0] = 5 instead 6 12 *nrc repeat sub - loop 0, use ba[2:0] = 6 instead 7 14 *nrc repeat sub - loop 0, use ba[2:0] = 7 instead note s : 1. dm must be driven low all the time. dqs, dqs# are mid - level . 2. dq signals are mid - level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 126 - table 4 2 C i dd 1 measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 act 0 0 1 1 0 0 0 0 0 0 0 - 1, 2 d, d 1 0 0 0 0 0 0 0 0 0 0 - 3, 4 d#, d# 1 1 1 1 0 0 0 0 0 0 0 - ... repeat pattern 1...4 until nr cd - 1, truncate if necessary nr cd rd 0 1 0 1 0 0 0 0 0 0 0 0000000 0 ... repeat pattern 1...4 until n ras - 1, truncate if necessary nr as pre 0 0 1 0 0 0 0 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 0 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 0 0 0 f 0 - 1*nrc+ 3 , 4 d#, d# 1 1 1 1 0 0 0 0 0 f 0 - ... repeat pattern nrc + 1,... ,4 until nrc + nr cd - 1, truncate if necessary 1*nrc+nr cd rd 0 1 0 1 0 0 0 0 0 f 0 00 11 00 11 ... repeat pattern nrc + 1,...,4 until nrc + nr as - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 0 0 0 f 0 - ... repeat pattern nrc + 1,...,4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub - loop 0, use ba[2:0] = 1 instead 2 4 *nrc repeat sub - loop 0, use ba[2:0] = 2 instead 3 6 *nrc repeat sub - loop 0, use ba[2:0] = 3 instead 4 8 *nrc repeat sub - loop 0, use ba[2:0] = 4 instead 5 10 *nrc repeat sub - loop 0, use ba[2:0] = 5 instead 6 12 *nrc repeat sub - loop 0, use ba[2:0] = 6 instead 7 14 *nrc repeat sub - loop 0, use ba[2:0] = 7 instead note s : 1. dm must be driven low all the time. dqs, dqs# are used according to rd commands, otherwise mid - level . 2. burst sequence driven on each dq signal by read command. outside burst operation, dq signals are mid - level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 127 - table 4 3 C i dd 2n and i dd3n measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 d 1 0 0 0 0 0 0 0 0 0 0 - 1 d 1 0 0 0 0 0 0 0 0 0 0 - 2 d# 1 1 1 1 0 0 0 0 0 f 0 - 3 d# 1 1 1 1 0 0 0 0 0 f 0 - 1 4 - 7 repeat sub - loop 0, use ba[2:0] = 1 instead 2 8 - 11 repeat sub - loop 0, use ba[2:0] = 2 instead 3 12 - 1 5 repeat sub - loop 0, use ba[2:0] = 3 instead 4 16 - 1 9 repeat sub - loop 0, use ba[2:0] = 4 instead 5 20 - 23 repeat sub - loop 0, use ba[2:0] = 5 instead 6 24 - 27 repeat sub - loop 0, use ba[2:0] = 6 instead 7 28 - 31 repeat sub - loop 0, use ba[2:0] = 7 instead note s : 1. dm must be driven low all the time. dqs, dqs# are mid - level . 2. dq signals are mid - level . table 4 4 C i dd 2nt and i dd q2 n t measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 d 1 0 0 0 0 0 0 0 0 0 0 - 1 d 1 0 0 0 0 0 0 0 0 0 0 - 2 d# 1 1 1 1 0 0 0 0 0 f 0 - 3 d# 1 1 1 1 0 0 0 0 0 f 0 - 1 4 - 7 repeat sub - loop 0, but odt = 0 and ba[2:0] = 1 2 8 - 11 repeat sub - loop 0, but odt = 1 and ba[2:0] = 2 3 12 - 1 5 repeat sub - loop 0, but odt = 1 and ba[2:0] = 3 4 16 - 1 9 repeat sub - loop 0, but odt = 0 and ba[2:0] = 4 5 20 - 23 repeat sub - loop 0, but odt = 0 and ba[2:0] = 5 6 24 - 27 repeat sub - loop 0, but odt = 1 and ba[2:0] = 6 7 28 - 31 repeat sub - loop 0, but odt = 1 and ba[2:0] = 7 note s : 1. dm must be driven low all the time. dqs, dqs# are mid - level . 2. dq signals are mid - level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 128 - table 4 5 C i dd4r and i ddq4r measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 rd 0 1 0 1 0 0 0 0 0 0 0 00000000 1 d 1 0 0 0 0 0 0 0 0 0 0 - 2, 3 d#, d# 1 1 1 1 0 0 0 0 0 0 0 - 4 rd 0 1 0 1 0 0 0 0 0 f 0 00 11 00 11 5 d 1 0 0 0 0 0 0 0 0 f 0 - 6, 7 d#, d# 1 1 1 1 0 0 0 0 0 f 0 - 1 8 - 15 repeat sub - loop 0, but ba[2:0] = 1 2 16 - 23 repeat sub - loop 0, but ba[2:0] = 2 3 24 - 31 repeat sub - loop 0, but ba[2:0] = 3 4 32 - 39 repeat sub - loop 0, but ba[2:0] = 4 5 40 - 47 repeat sub - loop 0, but ba[2:0] = 5 6 48 - 55 repeat sub - loop 0, but ba[2:0] = 6 7 56 - 63 repeat sub - loop 0, but ba[2:0] = 7 note s : 1. dm must be driven low all the time. dqs, dqs# are used according to rd commands, otherwise mid - level. 2. burst sequence driven on each dq signal by read command. outside burst operation, dq signals are mid - level . table 4 6 C i dd4w measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 wr 0 1 0 0 1 0 0 0 0 0 0 00000000 1 d 1 0 0 0 1 0 0 0 0 0 0 - 2, 3 d#, d# 1 1 1 1 1 0 0 0 0 0 0 - 4 wr 0 1 0 0 1 0 0 0 0 f 0 00 11 00 11 5 d 1 0 0 0 1 0 0 0 0 f 0 - 6, 7 d#, d# 1 1 1 1 1 0 0 0 0 f 0 - 1 8 - 15 repeat sub - loop 0, but ba[2:0] = 1 2 16 - 23 repeat sub - loop 0, but ba[2:0] = 2 3 24 - 31 repeat sub - loop 0, but ba[2:0] = 3 4 32 - 39 repeat sub - loop 0, but ba[2:0] = 4 5 40 - 47 repeat sub - loop 0, but ba[2:0] = 5 6 48 - 55 repeat sub - loop 0, but ba[2:0] = 6 7 56 - 63 repeat sub - loop 0, but ba[2:0] = 7 note s : 1. dm must be driven low all the time. dqs, dqs# are used according to wr commands, otherwise mid - level. 2. burst sequence driven on each dq signal by write command. outside burst operation, dq signals are mid - level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 129 - table 4 7 C i dd 5b measurement - loop pattern 1 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 1 1, 2 d, d 1 0 0 0 0 0 0 0 0 0 0 - 3, 4 d#, d# 1 1 1 1 0 0 0 0 0 f 0 - 5 ... 8 repeat cycles 1...4, but ba[2:0] = 1 9 ... 1 2 repeat cycles 1...4, but ba[2:0] = 2 13 ... 16 repeat cycles 1...4, but ba[2:0] = 3 17 ... 20 repeat cycles 1...4, but ba[2:0] = 4 2 1 ... 24 repeat cycles 1...4, but ba[2:0] = 5 2 5 ... 28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc - 1 repeat sub - loop 1, until nrfc - 1 . truncate, if necessary note s : 1. dm must be driven low all the time. dqs, dqs# are mid - level . 2. dq signals are mid - level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 130 - table 4 8 C i dd 7 measurement - loop pattern 1 attention: sub - loops 10 - 19 have inverse a[6:3] pattern and data pattern than sub - loops 0 - 9 ck, ck# cke sub - loop cycle number command cs# ras# cas# we# odt ba[2:0] a[14:11] a[10] a[9:7] a[ 6 : 3 ] a[2:0] data 2 toggling static high 0 0 act 0 0 1 1 0 0 0 0 0 0 0 - 1 rda 0 1 0 1 0 0 0 1 0 0 0 0000000 0 2 d 1 0 0 0 0 0 0 0 0 0 0 - ... repeat above d command until nrrd - 1 1 nr rd act 0 0 1 1 0 1 0 0 0 f 0 - nrrd+ 1 rda 0 1 0 1 0 1 0 1 0 f 0 00 11 00 11 nrrd+ 2 d 1 0 0 0 0 1 0 0 0 f 0 - ... repeat above d command until 2 * nrrd - 1 2 2 *nrrd repeat sub - loop 0, but ba[2:0] = 2 3 3 *nrrd repeat sub - loop 1 , but ba[2:0] = 3 4 4 *nrrd d 1 0 0 0 0 3 0 0 0 f 0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub - loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub - loop 1 , but ba[2:0] = 5 7 nfaw+ 2 *nrrd repeat sub - loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub - loop 1 , but ba[2:0] = 7 9 nfaw+ 4 *nrrd d 1 0 0 0 0 7 0 0 0 f 0 - assert and repeat above d command until 2 * nfaw - 1, if necessary 10 2*nfaw+ 0 act 0 0 1 1 0 0 0 0 0 f 0 - 2*nfaw+ 1 rda 0 1 0 1 0 0 0 1 0 f 0 00 11 00 11 2*nfaw+ 2 d 1 0 0 0 0 0 0 0 0 f 0 - repeat above d command until 2 * nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 0 0 0 0 0 - 2*nfaw+nrrd+ 1 rda 0 1 0 1 0 1 0 1 0 0 0 0000000 0 2*nfaw+nrrd+ 2 d 1 0 0 0 0 1 0 0 0 0 0 - repeat above d command until 2 * nfaw + 2 * nrrd - 1 12 2*nfaw+ 2 *nrrd repeat sub - loop 1 0, but ba[2:0] = 2 13 2*nfaw+ 3 *nrrd repeat sub - loop 11 , but ba[2:0] = 3 14 2*nfaw+ 4 *nrrd d 1 0 0 0 0 3 0 0 0 0 0 - assert and repeat above d command until 3 * nfaw - 1, if necessary 15 3 *nfaw repeat sub - loop 1 0, but ba[2:0] = 4 16 3 *nfaw+nrrd repeat sub - loop 11 , but ba[2:0] = 5 17 3 *nfaw+ 2 *nrrd repeat sub - loop 1 0, but ba[2:0] = 6 18 3 *nfaw+ 3 *nrrd repeat sub - loop 11 , but ba[2:0] = 7 19 3 *nfaw+ 4 *nrrd d 1 0 0 0 0 7 0 0 0 0 0 - assert and repeat above d command until 4 * nfaw - 1, if necessary note s : 1. dm must be driven low all the time. dqs, dqs# are used according to rd commands, otherwise mid - level . 2. burst sequence driven on each dq signal by read command. outside burst operation, dq signals are mid - level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 131 - 10.13.2 i dd current specifications speed bin ddr3 l - 1 333 ddr3 l - 1 600 ddr3 l - 1 866 sym. part number exten s ion - 1 5/15i - 1 2/12i - 1 1 unit definition m ax . m ax . m ax . i dd0 operating one bank active - precharge current 90 95 105 ma i dd1 operating one bank active - read - precharge current 110 115 125 ma i dd2 n precharge standby current 60 65 75 ma i dd2n t precharge standby odt current 90 95 100 ma i dd 2 p 0 precharge power down current slow exit 19 19 19 ma i dd 2p1 precharge power down current fast exit 48 50 55 ma i dd 2q precharge quiet standby current 60 65 70 ma i dd 3n active standby current 65 70 75 ma i dd 3p active power down current 50 55 60 ma i dd 4r operating burst read current 205 220 250 ma i dd 4w operating burst write current 180 200 230 ma i dd 5b burst refresh current 135 140 145 ma i dd 6 self - refresh current, t oper = 0 - 85c 19 19 19 ma i dd 6et self - refresh current, t oper = 0 - 95c 21 21 21 ma i dd 7 operating bank interleave read current 330 340 360 ma i dd 8 reset# low current 19 19 19 ma note s : 1. max. value s for i dd currents consider worst case conditions of process, temperature and voltage . 2. the i dd values must be derated (increased) when operated outside the range 0 c t case 85 c : (a) when t case < 0c: i dd2p0 , i dd2p1 and i dd3p must be derated by 4%; i dd4r and i dd5w must be derated by 2%; and i dd6 , i dd6et and i dd7 must be derated by 7%. (b) when t case > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 2%; and i dd2p 0 , i dd2p 1 must be der ated by 30%.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 132 - 10.14 clock specification the jitter specified is a random jitter meeting a gaussian distribution. input clocks violating the min/max values may result in malfunction of the ddr3l sdram device . definition for tck(avg) t ck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge . t ck ( avg ) = / n where n = 200 definition for tck(a bs ) t ck(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. t ck(abs) is not subject to production test . definition for tch(avg) and tcl(avg) t ch(avg) is defined as the average high pulse width, as calcula ted across any consecutive 200 high pulses . t ch ( avg ) = / ( n t ck ( avg )) where n = 200 t c l (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses . t cl ( avg ) = / ( n t ck ( avg )) where n = 200 definition for tjit(per) and tjit(per,lck) t jit(per) is defined as the largest deviation of any signal t ck from t ck(avg) . t jit(per) = min/max of {t ck i - t ck(avg) where i = 1 to 200}. t jit(per) defines the single period jitter when the dll is already locked. t jit(per,lck) uses the same definition for single period jitter, during the dll locking period only. t jit(per) and t jit (per,lck) are not subject to production test . ? ? ? ? ? ? ? ? n j j tck 1 ? ? ? ? ? ? ? ? n j j tch 1 ? ? ? ? ? ? ? ? n j j tcl 1
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 133 - definition for tjit(cc) and tjit(cc,lck) t jit(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. t jit(cc) = max of |{t ck i +1 - t ck i}|. t jit(cc) defines the cycle to cycle jitter when the dll is already locked. t jit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. t jit(cc) and t jit (cc,lck) are not subject to production test . definition for terr(nper) t err is defined as the cumulative error across n multiple consecutive cycles from t ck(avg) . t err is not subject to pr oduction test. 10.15 speed bins ddr3l sdram speed bins include t ck , t rcd , t rp , t rc and t r as for each corresponding bin. 10.15.1 ddr3l - 1 333 speed bin and operating conditions speed bin ddr3 l - 1 333 unit notes cl - nrcd - nrp 9 - 9 - 9 part number exten s ion - 15/15i parameter symbol m in . m ax . maximum operating frequency using maximum allowed settings for sup_cl and sup_cwl f ckmax ? 667 mhz internal read command to first data t aa 13. 5 (13.125) * 9 20 ns act to internal read or write delay time t rcd 13. 5 (13.125) * 9 ? ns pre command period t rp 13. 5 (13.125) * 9 ? ns act to act or ref command period t rc 49 . 5 ( 49 .125) * 9 ? ns act to pre command period t ras 36 9 * t refi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 4, 6 cwl = 6 , 7 t ck(avg) reserved ns 5 cl = 7 cwl = 5 t ck(avg) reserved ns 5 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 6 (optional) * 9 ns cwl = 7 t ck(avg) reserved ns 5 cl = 8 cwl = 5 t ck(avg) reserved ns 5 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 6 cwl = 7 t ck(avg) reserved ns 5 cl = 9 cwl = 5 , 6 t ck(avg) reserved ns 5 cwl = 7 t ck(avg) 1.5 < 1.875 ns 1, 2, 3, 4, 6 cl = 10 cwl = 5 , 6 t ck(avg) reserved ns 5 cwl = 7 t ck(avg) 1.5 < 1.875 ns 1, 2, 3, 4, 6 supported cl settings sup_cl 6, (7) , 8, 9 , 10 nck supported c w l settings sup_cwl 5, 6 , 7 nck n ote: field value contents in blue font or parentheses are optional ac parameter and cl setting . detail descriptions refer to note 9 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 134 - 10.15.2 ddr3l - 1 600 speed bin and operating conditions speed bin ddr3 l - 1 600 unit notes cl - nrcd - nrp 11 - 11 - 11 part number exten s ion - 12/12i parameter symbol m in . m ax . maximum operating frequency using maximum allowed settings for sup_cl and sup_cwl f ckmax ? 800 mhz internal read command to first data t aa 13. 7 5 (13.125) * 9 20 ns act to internal read or write delay time t rcd 13. 7 5 (13.125) * 9 ? ns pre command period t rp 13. 7 5 (13.125) * 9 ? ns act to act or ref command period t rc 48 . 7 5 ( 48 .125) * 9 ? ns act to pre command period t ras 35 9 * t refi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 4, 7 cwl = 6 , 7, 8 t ck(avg) reserved ns 5 cl = 7 cwl = 5 t ck(avg) reserved ns 5 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 7 (optional) * 9 ns 5 cwl = 7, 8 t ck(avg) reserved ns 5 cl = 8 cwl = 5 t ck(avg) reserved ns 5 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 7 cwl = 7 , 8 t ck(avg) reserved ns 5 cl = 9 cwl = 5 , 6 t ck(avg) reserved ns 5 cwl = 7 t ck(avg) 1.5 < 1.875 ns 5 (optional) * 9 ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 5 cl =10 cwl = 5 , 6 t ck(avg) reserved ns 5 cwl = 7 t ck(avg) 1.5 < 1.875 ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 5 cl =11 cwl = 5 , 6, 7 t ck(avg) reserved ns 5 cwl = 8 t ck(avg) 1. 2 5 < 1.5 ns 1, 2, 3, 4, 7 supported cl settings sup_cl 6, ( 7 ) , 8, ( 9 ) , 10 , 11 nck supported c w l settings sup_cwl 5, 6 , 7, 8 nck n ote: field value contents in blue font or parentheses are optional ac parameter and cl setting . detail descriptions refer to note 9 .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 135 - 10.15.3 ddr3 l - 1 866 speed bin and operating conditions speed bin ddr3 l - 1 866 unit notes cl - nrcd - nrp 13 - 13 - 13 part number exten s ion - 11 parameter symbol m in . m ax . maximum operating frequency using maximum allowed settings for sup_cl and sup_cwl f ckmax ? 933 mhz internal read command to first data t aa 13.91 20 ns act to internal read or write delay time t rcd 13.91 ? ns pre command period t rp 13.91 ? ns act to act or ref command period t rc 47 .91 ? ns act to pre command period t ras 34 9 * t refi ns cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 4, 8 cwl = 6 , 7, 8, 9 t ck(avg) reserved ns 5 cl = 8 cwl = 5 t ck(avg) reserved ns 5 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 8 cwl = 7 , 8, 9 t ck(avg) reserved ns 5 cl =10 cwl = 5 , 6 t ck(avg) reserved ns 5 cwl = 7 t ck(avg) 1.5 < 1.875 ns 1, 2, 3, 4, 8 cwl = 8 , 9 t ck(avg) reserved ns 5 cl =13 cwl = 5, 6 , 7, 8 t ck(avg) reserved ns 5 cwl = 9 t ck(avg) 1. 07 < 1.25 ns 1, 2, 3, 4, 8 supported cl settings sup_cl 6, 8, 10 , 13 nck supported c w l settings sup_cwl 5, 6 , 7, 9 nck
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 136 - 10.15.4 speed bin general notes the absolute specification for all speed bins is t oper and v dd = v ddq = 1.283v to 1.45v . in addition the following general notes apply . 1. max. limits are exclusive. e.g. if t ck(avg).max value is 2.5 ns, t ck(avg) needs to be < 2.5 ns. 2. the cl setting and cwl setting result in t ck(avg).min and t ck(avg).max requirements. when making a selection of t ck(avg) , both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 3. t ck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by t he dll - all possible intermediate frequencies may not be guaranteed. an application should use the next smaller standard t ck(avg) value ( 2.5 , 1.875 , 1.5 , 1.25 or 1. 07 n s ) when calculating cl [nck] = t aa [n s ] / t ck(avg) [n s ], rounding up to the next suppo rted cl. 4. t ck(avg).max limits: calculate t ck(avg) = t aa.max / cl selected and round the resulting t ck(avg) down to the next valid speed bin ( i.e. 3.3n s or 2.5n s or 1.875 n s , 1. 5 n s or 1. 2 5 n s ). this result is t ck(avg).max corresponding to cl selected. 5. reserved settings are not allowed. user must program a different value. 6. any ddr3l - 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterizati on. 7. any ddr3l - 1 600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 8. any ddr3 l - 1 866 speed bin also supports functional operation at low er frequencies as shown in the table which are not subject to production tests but verified by design/characterization . 9. for devices supporting optional down binning to cl=7 and cl=9, t aa /t rcd /t rp min must be 13.125 ns or lower. spd settings must be programmed to match. for example, ddr3l - 1333 (9 - 9 - 9) devices supporting down binning to ddr3l - 1066 (7 - 7 - 7) should program 13.125 ns in spd bytes for t aa min (byte 16), t rcd min (byte 18), and t rp min (byte 20). ddr3l - 1 600 (11 - 11 - 11) devices supporting down binning to ddr3l - 1333 (9 - 9 - 9) or ddr3l - 1066 (7 - 7 - 7) should program 13.125 ns in spd bytes for t aa min (byte16), t rcd min (byte 18), and t rp min (byte 20). once t rp (byte 20) is programmed to 13.125 ns, t rc min (byte 21, 2 3) also should be programmed accodingly. for example, 49.125n s (t ras min + t rp min = 36 n s + 13.125 n s ) for ddr3l - 1333 (9 - 9 - 9) and 48.125 ns (t ras min + t rp min = 35 ns + 13.125 ns) for ddr3l - 1600 (11 - 11 - 11).
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 137 - 10.16 ac characteristics 10.16.1 ac timing and o perating c ondition for - 11 speed grade s ym bol speed grade ddr3l - 1866 ( - 11) u nit s n otes p arameter m in . m ax . c ommon notes 1, 2, 3, 4 clock input timing t c k ( dll - off ) minimum clock cycle time (dll - off mode) 8 ? ns 45 t c k ( avg ) average clock period see speed bin on page 13 5 ps t ch ( avg ) average ck / ck# high pulse width 0.47 0.53 t ck (avg) t cl ( avg ) average ck / ck# low pulse width 0.47 0.53 t ck (avg) t c k ( a bs ) absolute clock period min.: t ck (avg)min + t jit (per)min max.: t ck (avg)max + t jit (per)max ps 37 t ch ( a bs ) absolute ck / ck# high pulse width 0.43 ? t ck (avg) 38 t cl ( a bs ) absolute ck / ck# low pulse width 0.43 ? t ck (avg) 39 t jit ( per ) clock period jitter - 60 60 ps t jit ( per,lck ) clock period jitter during dll locking period - 50 50 ps t jit ( cc ) cycle to cycle period jitter 120 ps t jit ( cc,lck ) cycle to cycle period jitter during dll locking period 100 ps t jit ( duty ) clock duty cycle jitter already included in t ch (abs) and t cl (abs) ps t err ( 2per ) cumulative error across 2 cycles - 88 88 ps t err ( 3 per ) cumulative error across 3 cycles - 105 105 ps t err ( 4 per ) cumulative error across 4 cycles - 117 117 ps t err ( 5 per ) cumulative error across 5 cycles - 126 126 ps t err ( 6 per ) cumulative error across 6 cycles - 133 133 ps t err ( 7 per ) cumulative error across 7 cycles - 139 139 ps t err ( 8 per ) cumulative error across 8 cycles - 145 145 ps t err ( 9 per ) cumulative error across 9 cycles - 150 150 ps t err ( 10 per ) cumulative error across 10 cycles - 154 154 ps t err ( 11 per ) cumulative error across 11 cycles - 158 158 ps t err ( 12 per ) cumulative error across 12 cycles - 161 161 ps t err ( n per ) cumul ative error across n = 13, 14... 49, 50 cycles min.: t jit (per)min * (1 + 0.68 * ln(n)) max.: t jit (per)max * (1 + 0.68 * ln(n)) ps 7
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 138 - ac timing and o perating c ondition for - 11 speed grade, continued s ym bol speed grade ddr3l - 1866 ( - 11) u nit s n otes p arameter m in . m ax . data timing t dqsq dqs, dqs# to dq skew, per group, per access ? qh dq output hold time from dqs, dqs# 0.38 ? ck (avg) 18, 23 t lz(dq) dq low impedance time from ck, ck# - 390 195 ps 17, 23, 24 t h z(dq) dq high impedance time from ck, ck# ? d s ( ac13 0 ) data setup time to dqs, dqs# base specification 70 ps 11 , 40 v ref @ 2 v/ns 135 ps 11 , 40, 42 t dh ( dc 9 0 ) data hold time from dqs, dqs# base specification 75 ps 11 , 40 v ref @ 2 v/ns 120 ps 11 , 40, 42 t dipw dq and dm input pulse width for each input 320 ? data strobe timing t rpre dqs,dqs# differential read preamble 0.9 note 21 t ck (avg) 18, 21, 23 t rpst dqs, dqs# differential read postamble 0.3 note 22 t ck (avg) 18, 22, 23 t qsh dqs,dqs# differential output high time 0.4 ? ck (avg) 18, 23 t qsl dqs,dqs# differential output low time 0.4 ? ck (avg) 18, 23 t wpre dqs,dqs# differential write preamble 0.9 ? ck (avg) 46 t wpst dqs,dqs# differential write postamble 0.3 ? ck (avg) 46 t dqsck dqs,dqs# rising edge out put access time from rising ck, ck# - 195 195 p s 17, 23 t lz(dqs) dqs and dqs# low - impedance time from ck, ck# (referenced from rl - 1) - 390 195 p s 17, 23, 24 t h z(dqs) dqs and dqs# high - impedance time from ck, ck# (referenced from rl + bl/2) ? dqsl dqs, dqs# differential input low pulse width 0.45 0.55 t ck (avg) 12, 14 t dqs h dqs,dqs# differential input high pulse width 0.45 0.55 t ck (avg) 13, 14 t dqss dqs,dqs# rising edge to ck,ck# rising edge - 0.27 0.27 t ck (avg) 16 t dss dqs,dqs# falling edge setup time to ck,ck# rising edge 0.18 ? ck (avg) 15, 16 t ds h dqs,dqs# falling edge hold time from ck,ck# rising edge 0.18 ? ck (avg) 15, 16 command and address timing t aa internal read command to first data see speed bin on page 13 r cd act to internal read or write delay time n s 8 t rp pre command period n s 8 t rc act to act or ref command period n s 8 t ras act to pre command period n s 8
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 139 - ac timing and o perating c ondition for - 11 speed grade, continued s ym bol speed grade ddr3l - 1866 ( - 11) u nit s n otes p arameter m in . m ax . command and address timing t dllk dll locking time 512 ? rtp internal read command to precharge command delay max(4nck, 7.5ns) ? wtr delay from start of internal write transaction to internal read command max(4nck, 7.5ns) ? wr write recovery time 15 ? mrd mode register set command cycle time 4 ? m o d mode register set command update delay max(12nck, 15ns) ? ccd cas# to cas# command delay 4 ? dal (min) auto precharge write recovery + precharge time wr + roundup(t rp (min) / t ck (avg) ) nck 6 t mprr multi - purpose register recovery time 1 ? rrd active to active command period for 1 kb page size max(4nck, 5 ns) ? faw four activate window for 1 kb page size 27 ? is(ac135) command and address setup time to ck, ck# base specification 65 ps 9 , 41 v ref @ 1 v/ns 200 ps 9 , 41, 42 t is (ac125) command and address setup time to ck, ck# base specification 150 ps 9 , 41 v ref @ 1 v/ns 275 ps 9 , 41, 42 t i h (dc 9 0) command and address hold time from ck, ck# base specification 1 1 0 ps 9 , 41 v ref @ 1 v/ns 200 ps 9 , 41, 42 t ipw control and address i nput pulse width for each input 535 ? calibration timing t zq init power - up and reset calibration time max(512nck, 640ns) ? zq oper normal operation full calibration time max( 256 nck, 320 ns) ? zqcs normal operation short calibration time max( 64 nck, 8 0ns) ? reset timing t xpr exit reset from cke high to a valid command max(5nck, 170 ns) ? self refresh timing t xs exit self refresh to commands not requiring a locked dll max(5nck, 170 ns) ? xsdll exit self refresh to commands requiring a locked dll t dllk (min) ? ckesr minimum cke low width for self refresh entry to exit timing t cke (min) + 1 nck ? cksre valid clock requirement after self refresh entry (sre) max(5 nck, 10 ns) ? cksrx valid clock requirement before self refresh exit (srx) max(5 nck, 10 ns) ? refresh timing t rfc ref command to act or ref command time 160 ? refi average periodic refresh interval 0 c cas e ? cas e ?
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 140 - ac timing and o perating c ondition for - 11 speed grade, continued s ym bol speed grade ddr3l - 1866 ( - 11) u nit s n otes p arameter m in . m ax . power down timing t xp exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll max( 3 nck, 6 ns) ? xpdll exit precharge power down with dll frozen to commands requiring a locked dll max( 10 nck, 24 ns) ? cke cke minimum pulse width max( 3 nck, 5 ns) ? cpded command pass disable delay 2 ? pd power down entry to exit timing t cke (min) 9 * t refi 25 t actpden timing of act command to power down entry 1 ? prpden timing of pre or prea command to power down entry 1 ? rdpden timing of rd/rda command to power down entry rl + 4 + 1 ? wrpden timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) min.: wl + 4 + roundup (t wr (min)/ t ck (avg)) max.: ? wrapden timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) min.: wl + 4 + wr + 1 max.: ? wrpden timing of wr command to power down entry (bc4mrs) min.: wl + 2 + roundup (t wr (min)/ t ck (avg)) max.: ? wrapden timing of wra command to power down entry (bc4mrs) min.: wl + 2 + wr + 1 max.: ? refpden timing of ref command to power down entry 1 ? mrspden timing of mrs command to power down entry t mod (min) ? odt timing odth4 odt high time without write command or with write command and burst chop 4 4 ? ? aonpd asynchronous r tt turn - on delay (power down with dll frozen) 2 8.5 n s 32 t aofpd asynchronous r tt turn - o ff delay (power down with dll frozen) 2 8.5 ns 32 t aon r tt turn - on - 195 195 ps 17, 43 t aof r tt _nom and r tt _wr turn - off time from odtloff reference 0.3 0.7 t ck (avg) 17, 44 t adc r tt dynamic change skew 0.3 0.7 t ck (avg) 17 write leveling timing t wlmrd first dqs/dqs# rising edge after write leveling mode is programmed 40 ? wldqsen dqs/dqs# delay after write leveling mode is programmed 25 ? wls write leveling setup time from ( ck, ck# ) zero crossing to rising ( dqs, dqs# ) zero crossing 140 ? wlh write leveling hold time from rising ( dqs, dqs# ) zero crossing to ( ck, ck# ) zero crossing 140 ? wlo write leveling output delay 0 7.5 ns t wloe write leveling output error 0 2 n s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 141 - 10.16.2 ac timing and o perating c ondition for - 12/12i / - 15/15i speed grades s ym bol speed grade ddr3l - 1600 ( - 12/12i ) ddr3l - 1333 ( - 15/15i ) u nit s n otes p arameter m in . m ax . m in . m ax . c ommon notes 1, 2, 3, 4 clock input timing t c k ( dll - off ) minimum clock cycle time (dll - off mode) 8 ? 8 ? ns 45 t c k ( avg ) average clock period see speed bin on page 13 4 see speed bin on page 1 3 3 ps t ch ( avg ) average ck / ck# high pulse width 0.47 0.53 0.47 0.53 t ck (avg) t cl ( avg ) average ck / ck# low pulse width 0.47 0.53 0.47 0.53 t ck (avg) t c k ( a bs ) absolute clock period min.: t ck (avg)min + t jit (per)min max.: t ck (avg)max + t jit (per)max ps 37 t ch ( a bs ) absolute ck / ck# high pulse width 0.43 ? 0.43 ? t ck (avg) 38 t cl ( a bs ) absolute ck / ck# low pulse width 0.43 ? 0.43 ? t ck (avg) 39 t jit ( per ) clock period jitter - 70 70 - 80 80 ps t jit ( per,lck ) clock period jitter during dll locking period - 60 60 - 70 70 ps t jit ( cc ) cycle to cycle period jitter 14 0 16 0 ps t jit ( cc,lck ) cycle to cycle period jitter during dll locking period 12 0 14 0 ps t jit ( duty ) clock duty cycle jitter already included in t ch (abs) and t cl (abs) ps t err ( 2per ) cumulative error across 2 cycles - 103 103 - 118 1 18 ps t err ( 3 per ) cumulative error across 3 cycles - 122 1 22 - 140 1 40 ps t err ( 4 per ) cumulative error across 4 cycles - 136 1 36 - 155 1 55 ps t err ( 5 per ) cumulative error across 5 cycles - 147 1 47 - 168 1 68 ps t err ( 6 per ) cumulative error across 6 cycles - 155 1 55 - 177 1 77 ps t err ( 7 per ) cumulative error across 7 cycles - 163 163 - 186 1 86 ps t err ( 8 per ) cumulative error across 8 cycles - 169 1 69 - 193 1 93 ps t err ( 9 per ) cumulative error across 9 cycles - 175 1 75 - 200 200 ps t err ( 10 per ) cumulative error across 10 cycles - 180 1 80 - 205 205 ps t err ( 11 per ) cumulative error across 11 cycles - 184 1 84 - 210 210 ps t err ( 12 per ) cumulative error across 12 cycles - 188 1 88 - 215 215 ps t err ( n per ) cumul ative error across n = 13, 14... 49, 50 cycles min.: t jit (per)min * (1 + 0.68 * ln(n)) max.: t jit (per)max * (1 + 0.68 * ln(n)) ps 7
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 142 - ac timing and o perating c ondition for - 12/12i / - 15/15i speed grades, continued s ym bol speed grade ddr3l - 1600 ( - 12/12i ) ddr3l - 1333 ( - 15/15i ) u nit s n otes p arameter m in . m ax . m in . m ax . data timing t dqsq dqs, dqs# to dq skew, per group, per access ? ? qh dq output hold time from dqs, dqs# 0.38 ? ? ck (avg) 18, 23 t lz(dq) dq low impedance time from ck, ck# - 450 225 - 500 250 ps 17, 23, 24 t h z(dq) dq high impedance time from ck, ck# ? ? ds( ac1 35 ) data setup time to dqs, dqs# base specification 25 45 ps 11 , 40 v ref @ 1 v/ns 160 180 11 , 40, 42 t dh (dc 9 0) data hold time from dqs, dqs# base specification 5 5 75 ps 11 , 40 v ref @ 1 v/ns 145 165 11 , 40, 42 t dipw dq and dm i nput pulse width for each input 360 ? ? data strobe timing t rpre dqs,dqs# differential read preamble 0.9 note 21 0.9 note 21 t ck (avg) 18, 21, 23 t rpst dqs, dqs# differential read postamble 0.3 note 22 0.3 note 22 t ck (avg) 18, 22, 23 t qsh dqs,dqs# differential output high time 0.4 ? ? ck (avg) 18, 23 t qsl dqs,dqs# differential output low time 0.4 ? ? ck (avg) 18, 23 t wpre dqs,dqs# differential write preamble 0.9 ? ? ck (avg) 46 t wpst dqs,dqs# differential write postamble 0.3 ? ? ck (avg) 46 t dqsck dqs,dqs# rising edge out put access time from rising ck, ck# - 225 225 - 255 255 p s 17, 23 t lz(dqs) dqs and dqs# low - impedance time from ck, ck# (referenced from rl - 1) - 450 225 - 500 250 p s 17, 23, 24 t h z(dqs) dqs and dqs# high - impedance time from ck, ck# (referenced from rl + bl/2) ? ? dqsl dqs, dqs# differential input low pulse width 0.45 0.55 0.45 0.55 t ck (avg) 12, 14 t dqs h dqs,dqs# differential input high pulse width 0.45 0.55 0.45 0.55 t ck (avg) 13, 14 t dqss dqs,dqs# rising edge to ck,ck# rising edge - 0.27 0.27 - 0.25 0.25 t ck (avg) 16 t dss dqs,dqs# falling edge setup time to ck,ck# rising edge 0.18 ? ? ck (avg) 15, 16 t ds h dqs,dqs# falling edge hold time from ck,ck# rising edge 0.18 ? ? ck (avg) 15, 16 command and address timing t aa internal read command to first data see speed bin on see speed bin on r cd act to internal read or write delay time n s 8 t rp pre command period n s 8 t rc act to act or ref command period n s 8 t ras act to pre command perio d n s 8 t dllk dll locking time 512 ? ? rtp internal read command to precharge command delay max(4nck, 7.5ns) ? ? wtr delay from start of internal write transaction to internal read command max(4nck, 7.5ns) ? ?
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 143 - ac timing and o perating c ondition for - 12/12i / - 15/15i speed grades, continued s ym bol speed grade ddr3l - 1600 ( - 12/12i ) ddr3l - 1333 ( - 15/15i ) u nit s n otes p arameter m in . m ax . m in . m ax . command and address timing t wr write recovery time 15 ? ? mrd mode register set command cycle time 4 ? ? m o d mode register set command update delay max(12nck, 15ns) ? ? ccd cas# to cas# command delay 4 ? ? dal (min) auto precharge write recovery + precharge time wr + roundup(t rp (min) / t ck (avg) ) nck 6 t mprr multi - purpose register recovery time 1 ? ? rrd active to active command period for 1 kb page size max(4nck, 6 ns) ? ? faw four activate window for 1 kb page size 30 ? ? is (ac1 60 ) command and address setup time to ck, ck# base specification 60 80 ps 9 , 41 v ref @ 1 v/ns 220 240 ps 9 , 41, 42 t is( ac1 35 ) command and address setup time to ck, ck# base specification 185 205 ps 9 , 41 v ref @ 1 v/ns 320 340 ps 9 , 41, 42 t i h ( d c 9 0 ) command and address hold time from ck, ck# base specification 130 150 ps 9 , 41 v ref @ 1 v/ns 220 240 ps 9 , 41, 42 t ipw control , a ddress and control i nput pulse width for each input 560 ? ? calibration timing t zq init power - up and reset calibration time max(512nck, 640ns) ? ? zq oper normal operation full calibration time max( 256 nck, 320 ns) ? ? zqcs normal operation short calibration time max( 64 nck, 8 0ns) ? ? reset timing t xpr exit reset from cke high to a valid command max(5nck, 170 ns) ? ? self refresh timing t xs exit self refresh to commands not requiring a locked dll max(5nck, 170 ns) ? ? xsdll exit self refresh to commands requiring a locked dll t dllk (min) ? dllk (min) ? ckesr minimum cke low width for self refresh entry to exit timing t cke (min) + 1 nck ? cke (min) + 1 nck ? cksre valid clock requirement after self refresh entry (sre) max(5 nck, 10 ns) ? ? cksrx valid clock requirement before self refresh exit (srx) max(5 nck, 10 ns) ? ? refresh timing t rfc ref command to act or ref command time 160 ? ? refi average periodic refresh interval - 4 0 c cas e ? ? cas e ? ? cas e ? t cas e 85 c is for 12i and 15i grade only .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 144 - ac timing and o perating c ondition for - 12/12i / - 15/15i speed grades, continued s ym bol speed grade ddr3l - 1600 ( - 12/12i ) ddr3l - 1333 ( - 15/15i ) u nit s n otes p arameter m in . m ax . m in . m ax . power down timing t xp exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll max( 3 nck, 6 ns) ? ? xpdll exit precharge power down with dll frozen to commands requiring a locked dll max( 10 nck, 24 ns) ? ? cke cke minimum pulse width max( 3 nck, 5 ns) ? ? cpded command pass disable delay 1 ? ? pd power down entry to exit timing t cke (min) 9 * t refi t cke (min) 9 * t refi 25 t actpden timing of act command to power down entry 1 ? ? prpden timing of pre or prea command to power down entry 1 ? ? rdpden timing of rd/rda command to power down entry rl + 4 + 1 ? ? wrpden timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) min.: wl + 4 + roundup (t wr (min)/ t ck (avg)) max.: ? wrapden timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) min.: wl + 4 + wr + 1 max.: ? wrpden timing of wr command to power down entry (bc4mrs) min.: wl + 2 + roundup (t wr (min)/ t ck (avg)) max.: ? wrapden timing of wra command to power down entry (bc4mrs) min.: wl + 2 + wr + 1 max.: ? refpden timing of ref command to power down entry 1 ? ? mrspden timing of mrs command to power down entry t mod (min) ? mod (min) ? odt timing odth4 odt high time without write command or with write command and burst chop 4 4 ? ? ? ? aonpd asynchronous r tt turn - on delay (power down with dll frozen) 2 8.5 2 8.5 n s 32 t aofpd asynchronous r tt turn - o ff delay (power down with dll frozen) 2 8.5 2 8.5 ns 32 t aon r tt turn - on - 225 225 - 250 250 ps 17, 43 t aof r tt _nom and r tt _wr turn - off time from odtloff reference 0.3 0.7 0.3 0.7 t ck (avg) 17, 44 t adc r tt dynamic change skew 0.3 0.7 0.3 0.7 t ck (avg) 17 write leveling timing t wlmrd first dqs/dqs# rising edge after write leveling mode is programmed 40 ? ? wldqsen dqs/dqs# delay after write leveling mode is programmed 25 ? ? wls write leveling setup time from ( ck, ck# ) zero crossing to rising ( dqs, dqs# ) zero crossing 165 ? ? wlh write leveling hold time from rising ( dqs, dqs# ) zero crossing to ( ck, ck# ) zero crossing 165 ? ? wlo write leveling output delay 0 7.5 0 9 ns t wloe write leveling output error 0 2 0 2 n s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 145 - 10.16.3 timing parameter notes 1. unit t ck( avg) represents the actual t ck (avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, c ounting the actual clock edges. for example, t mrd = 4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm+4, even if (tm+4 - tm) is 4 x t ck (avg) + t err (4per),min (which is smaller than 4 x t ck (avg)). 2. timing that is not specified is illegal and after such an event, in order to provide proper operation, the dram must be resetted or powered down and then restarted through the specified initialization sequence before normal operation can continue . 3. the ck/ck# input reference level (for timing reference to ck / ck#) is the point at which ck and ck # cross . the dqs/dqs# input reference level is the point at which dqs and dqs# cross; the input reference level for signals other tha n ck/ck#, dqs/dqs# and reset# is v refca and v refdq respectively. 4. inputs are not recognized as valid until v refca stabilizes within specified limits. 5. the max values are system dependent. 6. t ck (avg) refers to the actual application clock period. wr refers to t he wr parameter stored in mode register mr0. 7. n = from 13 cycles to 50 cycles. this row defines 38 parameters . 8. for these parameters, the ddr3l sdram device supports t nparam [nck] = ru{ t param [ns] / t ck (avg) [n s ] }, which is in clock cycles, assuming all in put clock jitter specifications are satisfied. for example, the device will support tn rp = ru{t rp / t ck (avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr3l - 1 333 ( 9 - 9 - 9 ), of which t rp = 13.5 ns, the device will support tn rp = ru{t rp / t ck (avg)} = 9 , as long as the input clock jitter specifications are met, i.e. precharge command at tm and active command at tm+ 9 is valid even if (tm+ 9 - tm) is less than 1 3.5 ns due to input clock jitter . 9. these parameter s are measured from a command/address signal (cke, cs#, ras#, cas#, we#, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit ( cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not . 10. pulse width of a input signal is defined as the width between the first crossing of v ref ( dc ) and the consecutive crossing of v ref ( dc ) . 11. these parameters are measured from a data signal ( dm, dq0, dq1 , etc.) transition edge to its respective data strobe signal ( dqs, dqs# ) crossing . 12. t dqsl describes the instantaneous differential input low pulse width on dqs - dqs#, as measured from one falling edge to the next consecutive rising edge. 13. t dqsh describes the instantaneous differential input high pulse width on dqs - dqs#, as measured from one rising edge to the next consecutive falling edge . 14. t dqsh ,act + t dqsl ,act = 1 t ck ,act ; with t xyz ,act being the actual measured value of the respective timing parameter in the application. 15. t dsh ,act + t dss ,act = 1 t ck ,act ; with t xyz ,act being the actual meas ured value of the respective timing parameter in the application. 16. these parameters are measured from a data strobe signal ( dqs, dqs# ) crossing to its respective clock signal (ck, ck#) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. t jit (per), t jit (cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 146 - 17. when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err (mper),act of the input clock, where 2 <= m <= 12. ( o utput deratings are relative to the actual sdram input clock.) for example, if the measured jitter into a ddr3l - 1333 sdram has t err (mper),act,min = - 1 38 ps and t err (mper),act,max = + 1 55 ps, then t dqsck, min(derated) = t dqsck ,min - t err (mper),act,max = - 255 ps - 1 55 ps = - 410 ps and t dqsck ,max(derated) = t dqsck ,max - t err (mper),act,mi n = 255 ps + 1 38 ps = + 393 ps . similarly, t lz(dq) for ddr3l - 1 333 derates to t lz(dq) ,min(derated) = - 50 0 ps - 1 55 ps = - 655 ps and t lz(dq ),max(derated) = 25 0 ps + 1 38 ps = + 388 ps . (caution on the min/max usage!) note that t err (mper),act,min is the minimum measured value of t err (nper) where 2 <= n <= 12, and t err (mper),act,max is the maximum measured value of t err (nper) where 2 <= n <= 12 . 18. when the device is operated with input clock jitter, this parameter needs to be derated by the actual t jit (per),act of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3l - 1 333 sdram has t ck (avg),act = 1 500 ps, t jit (per),act,min = - 58 ps and t jit (per),act,max = + 7 4 ps, then t rpre ,min(derated) = t rpre ,min + t jit (per),act,min = 0.9 x t ck (avg),act + t jit (per),act,min = 0.9 x 1 500 ps - 58 ps = + 1 292 ps . similarly, t qh ,min(derated) = t qh ,min + t jit (per),act,min = 0.3 8 x t ck (avg),act + t jit (per),act,min = 0.3 8 x 1 500 ps - 58 ps = + 512 ps . (caution on the min/max usage!) . 19. wr in clock cycles as programmed in mode register mr0 . 20. t wr (min) is defined in n s , for calculation of t wrpden it is necessary to round up t wr (min)/ t ck (avg) to the next integer value . 21. the maximum read preamble is bound by t lz(dqs ) min on the left side and t dqsck (max) on the right side . see figure 24 - read timing; clock to data strobe relationshi p on page 4 5 . 22. the maximum read postamble is bound by t dqsck (min) plus t qsh (min) on the left side and t hz (dqs) max on the right side . see figure 24 - read timing; clock to data strobe relationshi p on page 4 5 . 23. value is only valid for ron34. 24. single ended si gnal parameter. 25. t refi depends on t oper . 26. start of internal write transaction is defined as follows: for bl8 (fixed by mrs and on - the - fly): rising clock edge 4 clock cycles after wl. for bc4 (on - the - fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl . 27. cke is allowed to be registered low while operations such as row activation, precharge, auto - precharge or refresh are in progress, but power down i dd spec will not be applied until finishing those operations . 28. although cke is allowed to be registered low after a refresh command once t refpden (min) is satisfied, there are cases where additional time such as t xpdll (min) is also required . see section 8 .17.3 power - down clarifications - case 2 on page 7 5 . 29. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function . 30. odth4 is measured from odt first registered high (without a write command) to odt first registered low, or from odt registered high together with a write command with burst length 4 to odt registered low. 31. odth8 is measured from odt registered high together with a write command with burst length 8 to odt registere d low. 32. this parameter applies upon entry and during precharge power down mode with dll frozen.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 147 - 33. one zqcs command can effectively correct a minimum of 0.5 % (zq correction) of ron and r tt impedance error within 64 nck for all speed bins assuming the maximu m sensitivities specified in the output driver voltage and temperature sensitivity and odt voltage and temperature sensitivity tables. the appropriate interval between zqcs commands can be determined from these tables and other application - specific par ameters . one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / ? c , vsens = 0.15% / mv, tdriftrate = 1 ? c / sec and vdriftrate = 15 mv/ sec, then the interval between zqcs commands is calculated as: = 0.133 128ms 34. commands not requiring a locked dll are all commands except read, read with auto - precharge and synchronous odt. 35. commands requ iring a locked dll are read, read with auto - precharge and synchronous odt. 36. a maximum of one regular plus eight posted refresh commands can be issued to any given ddr3l sdram device meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 t refi . 37. parameter t ck (avg) is specified per its average value. however, it is understood that the relationship between the average timing t ck (avg) and the respective absolute instantaneous timing t ck (abs) holds all times. 38. t ch (abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 39. t cl (abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 40. t ds (base) and t dh (base) values are for a single - ended 1v/ns slew rate dqs (dqs are at 2v/n s for ddr3 l - 1866 ) and 2v/ns dqs, dqs# differential slew rate . note for dq and dm signals, v ref(dc) = v refdq(dc) . for input only pins except reset#, v ref(dc) = v refca(dc) . see section 10 .16. 5 data setup, hold and slew rate derating on page 1 55 . 41. t is (base) and t ih (base) values are for 1v/ns cmd/add single - ended slew rate and 2v/ns ck, ck# differential slew rate. note for dq and dm signals, v ref(dc) = v refdq(dc) . for inpu t only pins except reset#, v ref(dc) = v refca(dc) . see section 10 .16. 4 address / command setup, hold and derating on page 1 4 8 . 42. the setup and hold time s are listed converting the base specification values (to which derating tables apply) to v ref when the slew rate is 1 v/n s (dqs are at 2v/n s for ddr3 l - 1866) . these values, with a slew rate of 1 v/n s (dqs are at 2v/n s for ddr3 l - 1866) , are for reference only . 43. for definition of rtt turn - on time t aon see 8 .19.2.2 timing parameters on page 80 . 44. for definition of rtt turn - off time t aof see 8 .19.2.2 timing parameters on page 80 . 45. there is no maximum cycle time limit besides the need to satisfy the refresh interval, t refi . 46. actual value dependant upon measurement level definitions see figure 4 1 - method for calculating t wpre transitions and endpoints on page 5 8 and see figu re 4 2 - method for calculating t wpst transitions and endpoints on page 5 8 . ) vdriftrate (vsens + ) tdriftrate (tsens on zqcorrecti 15) (0.15 + 1) (1.5 0.5
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 148 - 10.16.4 address / command setup, hold and derating for all input signals the total t is (setup time) and t ih (hold time) required i s calculated by adding the data sheet t is(base) and t ih(base) value (see table 4 9 ) to the t is and t ih derating value (see table 50 to table 52 ) respectively. example: t is (total setup time) = t is(base) + t is setup (t is ) nominal slew rate for a rising signal is defined as the slew ra te between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (t is ) nominal slew rate for a falling signal is defined as the slew rat e between the last crossing of v ref(dc) and the first crossing of v il(ac) max. if the actual signal is always earlier than the nominal slew rate line between shaded v ref(dc) to ac region, use nominal slew rate for derating value (see figure 10 7 ). if the a ctual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 10 9 ). hold (t ih ) nominal slew rate for a rising signal is defined as the slew ra te between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (t ih ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc) min and the f irst crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded dc to v ref(dc) region, use nominal slew rate for derating value (see figure 10 8 ). if the actual signal is earlier than the nominal slew rate li ne anywhere between shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 1 10 ). for a valid transition the input signal has to remain above/below v ih/ il(ac) for some time t vac (see table 5 3 ). although for slow slew rates the total setup time might be negative (i.e. a v alid input signal will not have reached v ih/il(ac) at the time of the rising clock transition, a valid input signal is still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in the t able s , the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and ch aracterization . table 4 9 C add/cmd setup and hold base - values for 1v/ns symbol reference ddr3 l - 1 333 ddr3 l - 1 600 ddr3 l - 1 866 unit note t is(base) ac1 6 0 v ih/l(ac) : sr=1 v/n s 8 0 6 0 - ps 1 t i s (base) ac1 35 v ih/l(ac) : sr=1 v/n s 250 185 65 ps 1, 2 t i s (base) ac1 25 v ih/l(ac) : sr=1 v/n s - - 150 ps 1, 3 t i h (base) dc 9 0 v ih/l(dc) : sr=1 v/n s 1 5 0 1 3 0 1 1 0 ps 1 note s : 1. (ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck - ck# slew rate) 2. the t is(base) ac1 35 specifications are adjusted from the t is(base) ac1 60 specification by adding an additional 1 00 ps for ddr3l - 1333 /1600 of derating to accommodate for the lower alternate threshold of 1 35 mv and another 25 ps to account for the earlier reference point [(1 60 mv - 1 35 mv) / 1 v/ns] . 3. the t is(base) ac1 2 5 specifications are adjusted from the t is(base) ac1 35 specification by adding an additional 75 ps for ddr3 l - 1 866 of derating to accommodate for the lower alternate threshold of 1 35 mv and another 10 ps to account for the earlier reference point [(1 35 mv - 1 2 5 mv) / 1 v/ns].
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 149 - table 50 C derating values ddr3l - 1 333 t is /t ih - ac/dc based cmd/ add slew rate (v/ns) t i s, t ih derating in [ps] ac/dc based ac1 60 threshold - > vih(ac)=vref(dc)+ 1 60 mv , vil(ac)=vref(dc) - 1 60 mv ck, ck# differential slew rate 4 .0 v/ns 3 .0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1 .0 v/ns t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih 2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 - 1 - 3 - 1 - 3 - 1 - 3 7 5 15 13 23 21 31 31 39 47 0.8 - 3 - 8 - 3 - 8 - 3 - 8 5 1 13 9 21 17 29 27 37 43 0.7 - 5 - 13 - 5 - 13 - 5 - 13 3 - 5 11 3 19 11 27 21 35 37 0.6 - 8 - 20 - 8 - 20 - 8 - 20 0 - 12 8 - 4 16 4 24 14 32 30 0.5 - 20 - 30 - 20 - 30 - 20 - 30 - 12 - 22 - 4 - 14 4 - 6 12 4 20 20 0.4 - 40 - 45 - 40 - 45 - 40 - 45 - 32 - 37 - 24 - 29 - 16 - 21 - 8 - 11 0 5 table 5 1 C derating values ddr3l - 1 333 t is /t ih - ac/dc based - alternate ac1 35 threshold cmd/ add slew rate (v/ns) t i s, t ih derating in [ps] ac/dc based alternate ac1 35 threshold - > vih(ac)=vref(dc)+ 1 35 mv , vil(ac)=vref(dc ) - 1 35 mv ck, ck# differential slew rate 4 .0 v/ns 3 .0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1 .0 v/ns t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih 2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95 1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 - 3 2 - 3 2 - 3 10 5 18 13 26 21 34 31 42 47 0.8 3 - 8 3 - 8 3 - 8 11 1 19 9 27 17 35 27 43 43 0.7 6 - 13 6 - 13 6 - 13 14 - 5 22 3 30 11 38 21 46 37 0.6 9 - 20 9 - 20 9 - 20 17 - 12 25 - 4 33 4 41 14 49 30 0.5 5 - 30 5 - 30 5 - 30 13 - 22 21 - 14 29 - 6 37 4 45 20 0.4 - 3 - 45 - 3 - 45 - 3 - 45 6 - 37 14 - 29 22 - 21 30 - 11 38 5
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 150 - table 5 2 C derating values ddr3 l - 1 866 t is /t ih - ac/dc based alternate ac1 25 threshold cmd/ add slew rate (v/ns) t i s, t ih derating in [ps] ac/dc based alternate ac1 2 5 threshold - > vih(ac)=vref(dc)+1 2 5mv, vil(ac)=vref(dc) - 1 2 5mv ck, ck# differential slew rate 4 .0 v/ns 3 .0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1 .0 v/ns t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih t i s t ih 2.0 63 45 63 45 63 45 71 5 3 79 6 1 87 69 95 79 103 95 1.5 42 3 0 42 3 0 42 3 0 50 38 58 46 66 5 4 74 6 4 82 8 0 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 3 - 3 3 - 3 3 - 3 1 1 5 19 1 3 2 7 2 1 3 5 3 1 4 3 4 7 0.8 6 - 8 6 - 8 6 - 8 14 1 22 9 30 1 7 38 2 7 46 4 3 0.7 1 0 - 1 3 1 0 - 1 3 1 0 - 1 3 1 8 - 5 2 6 3 3 4 11 4 2 21 5 0 37 0.6 16 - 2 0 16 - 2 0 16 - 2 0 24 - 1 2 32 4 40 - 4 48 14 56 30 0.5 15 - 3 0 15 - 3 0 15 - 3 0 23 - 2 2 31 - 1 4 39 - 6 47 4 55 2 0 0.4 13 - 45 13 - 45 13 - 45 21 - 37 29 - 29 37 - 21 45 - 11 53 5 table 53 C required time t vac above v ih(ac) {below v il(ac) } for valid add/cmd transition slew rate [v/ns] ddr3l - 1333/1600 ddr3l - 1866 t vac @ 1 60 mv [ps] t vac @ 1 35 mv [ps] t vac @ 1 35 mv [ps] t vac @ 1 25 mv [ps] m in . m ax . m in . m ax . m in . m ax . m in . m ax . > 2.0 200 - 213 - 200 - 205 - 2.0 200 - 213 - 200 - 205 - 1.5 173 - 190 - 178 - 184 - 1 .0 120 - 145 - 133 - 143 - 0.9 102 - 130 - 118 - 129 - 0.8 80 - 111 - 99 - 111 - 0.7 51 - 87 - 75 - 89 - 0.6 13 - 55 - 43 - 59 - 0.5 note - 10 - note - 18 - < 0.5 note - 10 note - 18 - note: rising input signal shall become equal to or greater than v ih( ac ) level and falling input signal shall become equal to or less than v il( ac ) level.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 151 - figure 10 7 C illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) c k c k # d q s # d q s v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t i s t i h t i s t i h t v a c n o m i n a l s l e w r a t e v r e f t o a c r e g i o n n o m i n a l s l e w r a t e v r e f t o a c r e g i o n t v a c t f t r s e t u p s l e w r a t e f a l l i n g s i g n a l = v r e f ( d c ) C v i l ( a c ) m a x t f s e t u p s l e w r a t e r i s i n g s i g n a l = v i h ( a c ) m i n - v r e f ( d c ) t r t d s t d h t d s t d h n o t e : c l o c k a n d s t r o b e a r e d r a w n o n a d i f f e r e n t t i m e s c a l e .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 152 - figure 10 8 C illustration of nominal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock) v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t i s t i h t i s t i h n o m i n a l s l e w r a t e d c t o v r e f r e g i o n n o m i n a l s l e w r a t e d c t o v r e f r e g i o n t f t r t d s t d h t d s t d h n o t e : c l o c k a n d s t r o b e a r e d r a w n o n a d i f f e r e n t t i m e s c a l e . h o l d s l e w r a t e r i s i n g s i g n a l = v r e f ( d c ) C v i l ( d c ) m a x t r h o l d s l e w r a t e f a l l i n g s i g n a l = v i h ( d c ) m i n - v r e f ( d c ) t f c k c k # d q s # d q s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 153 - figure 10 9 C illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r v r e f t o a c r e g i o n v r e f t o a c r e g i o n t a n g e n t l i n e t a n g e n t l i n e n o m i n a l l i n e n o m i n a l l i n e t v a c t v a c s e t u p s l e w r a t e r i s i n g s i g n a l = t a n g e n t l i n e [ v i h ( a c ) m i n - v r e f ( d c ) ] t r s e t u p s l e w r a t e f a l l i n g s i g n a l = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] t f t i s t i h t i s t i h t d s t d h t d s t d h n o t e : c l o c k a n d s t r o b e a r e d r a w n o n a d i f f e r e n t t i m e s c a l e . c k c k # d q s # d q s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 154 - figure 1 10 C illustration of tangent line for for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock) v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r d c t o v r e f r e g i o n t a n g e n t l i n e n o m i n a l l i n e h o l d s l e w r a t e r i s i n g s i g n a l = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( d c ) m a x ] t r d c t o v r e f r e g i o n t a n g e n t l i n e n o m i n a l l i n e h o l d s l e w r a t e f a l l i n g s i g n a l = t a n g e n t l i n e [ v i h ( d c ) m i n - v r e f ( d c ) ] t f t i s t i h t i s t i h t d s t d h t d s t d h n o t e : c l o c k a n d s t r o b e a r e d r a w n o n a d i f f e r e n t t i m e s c a l e . c k c k # d q s # d q s v d d q
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 155 - 10.16.5 data setup, hold and slew rate derating for all input signals the total t ds (setup time) and t dh (hold time) requi red is calculated by adding the data sheet t ds(base) and t dh(base) value (see table 5 4 ) to t he t ds and t dh ( see table 55 and table 56 ) derating value respectively. example: t ds (total setup time) = t ds(base) + t ds . setup (t ds ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac) min. setup (t ds ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac) max (see figure 10 7 ). if the actual signal is always earlier than the nominal slew rate line between shaded v ref(dc) to ac region, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent lin e to the actual signal from the ac level to dc level is used for derating value (see figure 1 0 9 ). hold (t dh ) nominal slew rate for a rising signal is defined as the slew ra te between the last crossing of v il(dc) max and the first crossing of v ref(dc) . hold (t dh ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc ) min and the first crossing of v ref(dc) (see figure 10 8 ). if the actual signal is always later than the nominal slew rate line betwe en shaded dc level to v ref(dc) region, use nominal slew rate for derating value. if the actual signal is ear lier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a ta ngent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 1 10 ). for a valid transition the input signal has to rem ain above/below v ih/il(ac) for some time t vac (see table 5 7 ). although for slow slew rates the total setup time might be negative (i.e. a v alid input signal will not have reached v ih/il(ac) at the time of the rising clock transition) a valid input signa l i s still required to complete the transition and reach v ih/il(ac) . for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verifi ed by design and characterization . table 5 4 C data setup and hold base - values symbol reference ddr3 l - 1 333 ddr3 l - 1 600 ddr3 l - 1 866 unit note t d s(base) ac1 35 v ih/l(ac) : sr=1 v/n s 45 25 ? ps 1 t d s(base) ac1 30 v ih/l(ac) : sr= 2 v/n s ? ? 70 ps 2 t d h(base) dc 9 0 v ih/l(dc) : sr=1 v/n s 7 5 5 5 ? ps 1 t d h(base) dc 9 0 v ih/l(dc) : sr= 2 v/n s ? ? 70 ps 2 note s : 1. (ac/dc referenced for 1v/ns dq - slew rate and 2 v/ns dqs slew rate) 2. (ac/dc referenced for 2 v/ns dq - slew rate and 4 v/ns dqs slew rate) .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 156 - table 5 5 C derating values for ddr3 l - 1 333 t ds /t dh - (ac1 35 ) dq slew rate (v/ns) t ds , t dh derating in [ps] ac/dc based * alternate ac1 3 5 threshold - > vih(ac)=vref(dc)+1 35 mv, vil(ac)=vref(dc) - 1 35 mv dqs, dqs# differential slew rate 4 .0 v/ns 3 .0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1 .0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 2.0 68 45 68 45 68 45 - - - - - - - - - - 1.5 45 30 45 30 45 30 53 38 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 2 - 3 2 - 3 10 5 18 13 26 21 - - - - 0.8 - - - - 3 - 8 11 1 19 9 27 17 35 27 - - 0.7 - - - - - - 14 - 5 22 3 30 11 38 21 46 37 0.6 - - - - - - - - 25 - 4 33 4 41 14 49 30 0.5 - - - - - - - - - - 29 - 6 37 4 45 20 0.4 - - - - - - - - - - - - 30 - 11 38 5 note: cell contents - are defined as not supported . table 5 6 C derating values for ddr3 l - 1 866 t ds /t dh - (ac1 3 0 ) dq slew rate (v/ns) t ds , t dh derating in [ps] ac/dc based * alternate ac1 3 0 threshold - > vih(ac)=vref(dc)+1 3 0 mv, vil(ac)=vref(dc) - 1 3 0 mv dqs, dqs# differential slew rate 8.0 v/ns 7.0 v/ns 6.0 v/ns 5 . 0 v/ns 4.0 v/ns 3 . 0 v/ns 2.0 v/ns 1.8 v/ns 1 . 6 v/ns 1.4 v/ns 1.2 v/ns 1 .0 v/ns t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh t ds t dh 4.0 3 3 2 3 3 3 2 3 3 3 2 3 - - - - - - - - - - - - - - - - - - 3.5 2 8 19 2 8 19 2 8 19 2 8 19 - - - - - - - - - - - - - - - - 3.0 2 2 1 5 2 2 1 5 2 2 1 5 2 2 1 5 2 2 1 5 - - - - - - - - - - - - - - 2.5 - - 1 3 9 1 3 9 1 3 9 1 3 9 1 3 9 - - - - - - - - - - - - 2.0 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - - 1.5 - - - - - - - 2 2 - 1 5 - 2 2 - 1 5 - 2 2 - 1 5 - 2 2 - 1 5 - 1 4 - 7 - - - - - - - - 1.0 - - - - - - - - - 6 5 - 45 - 6 5 - 45 - 6 5 - 45 - 57 - 37 - 49 - 29 - - - - - - 0.9 - - - - - - - - - - - 6 2 - 48 - 6 2 - 48 - 54 - 40 - 46 - 32 - 38 - 24 - - - - 0.8 - - - - - - - - - - - - - 6 1 - 53 - 53 - 45 - 45 - 37 - 37 - 29 - 29 - 19 - - 0.7 - - - - - - - - - - - - - - - 49 - 50 - 41 - 42 - 33 - 34 - 25 - 24 - 17 - 8 0.6 - - - - - - - - - - - - - - - - - 37 - 49 - 29 - 41 - 21 - 31 - 13 - 15 0.5 - - - - - - - - - - - - - - - - - - - 31 - 51 - 23 - 41 - 15 - 25 0.4 - - - - - - - - - - - - - - - - - - - - - 28 - 56 - 20 - 40 note: cell contents - are defined as not supported . table 57 C required time t vac above v ih(ac) {below v il(ac) } for valid transition slew rate [v/ns] ddr3l - 1333/1600 (ac 135) ddr3l - 1866 (ac 130) t vac [ps] t vac [ps] m in . m ax . m in . m ax . > 2.0 1 13 - 95 - 2.0 1 13 - 95 - 1.5 90 - 73 - 1 .0 45 - 30 - 0.9 30 - 16 - 0.8 11 - note - 0.7 note - - - 0.6 note - - - 0.5 note - - - < 0.5 note - - note: rising input signal shall become equal to or greater than v ih( ac ) level and falling input signal shall become equal to or less than v il( ac ) level .
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 157 - 11. backward compatible to 1.5v ddr3 sdram vdd/vddq requirements 11.1 input/ o utput f unctional s ymbol type function v dd supply power supply: ddr3l operation = 1.283v to 1.45 v; ddr3 operation = 1.425v to 1.575 v v ddq supply dq power supply: dd r3l operation = 1.283 v to 1.45v; ddr3 operation = 1.425 v to 1.575v 11.2 recommended dc operating conditions - ddr3l (1.35 v) operation s ymbol parameter/condition m in. t yp . m ax . u nit n otes v dd supply voltage 1. 283 1. 35 1. 45 v 1 , 2, 3, 4 v ddq supply voltage for output 1. 283 1. 35 1. 45 v 1 , 2, 3, 4 note s : 1. maximum dc value may not be greater than 1.425v. the dc value is the linear average of v dd /v ddq (t) over a very long period of time (e.g., 1 sec). 2. if maximum limit is exceeded, input levels shall be governed by ddr3 specifications. 3. under these supply voltages, the device operates to this ddr3l specifcation . 4. once initialized for ddr3l operation, ddr3 operation may only be used if the device is in reset w hile v dd and v ddq are changed for ddr3 operation (see figure 111). 11.3 recommended dc operating conditions - ddr3 (1.5 v) operation s ymbol parameter/condition m in. t yp . m ax . u nit n otes v dd supply voltage 1. 425 1. 5 1. 57 5 v 1 , 2, 3 v ddq supply voltage for output 1. 425 1. 5 1. 57 5 v 1 , 2, 3 note s : 1. if minimum limit is exceeded, input levels shall be governed by ddr3l specifications. 2. under 1.5 v operation, this ddr3l device operates to the ddr3 specifcations under the same speed timings as defined for this device . 3. once initialized for ddr3 operation, ddr3 l operation may only be used if the device is in reset while v dd and v ddq are changed for ddr3 l operation (see figure 111) . 11.4 v ddq /v ddq voltage switch b etween ddr3l and ddr3 if the sdram is powered up and init ialized for the 1.35v operating voltage range, voltage can be increased to the 1.5v operating range provided that: ? just prior to increasing the 1.35v operating voltages, no further commands are issued, other than nops or command inhibits, and all banks are in the precharge state. ? the 1.5v operating voltages are stable prior to issuing new commands, other than nops or command inhibits. ? the dll is reset and relocked after the 1.5v operating voltages are stable and prior to any read command. ? the zq calibration is performed. t zq init must be satisfied after the 1.5v operating voltages are stable and prior to any read command.
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 158 - if the sdram is powered up and initialized for the 1.5v operating voltage range, voltage can be reduced to the 1. 3 5v operating range provided that: ? just prior to reducing the 1.5v operating voltages, no further commands are issued, other than nops or command inhibits, and all banks are in the precharge state. ? the 1.35v operating voltages are stable prior to issuing new commands, other t han nops or command inhibits. ? the dll is reset and relocked after the 1.35v operating voltages are stable and prior to any read command. ? the zq calibration is performed. t zq init must be satisfied after the 1.35v operating voltages are stable and prior to a ny read command. after the ddr3l dram is powered up and initialized, the power supply can be altered between the ddr3l and ddr3 levels, provided the sequence in figure 111 is maintained. n ote : 1 . from time point td until tk nop or des commands must be applied between mrs and zqcl commands. figure 111 C v ddq /v ddq voltage switch b etween ddr3l and ddr3 t i m e b r e a k d o n ' t c a r e t a t b t c t d t e t f t g t h t i t j t k c k , c k # v d d , v d d q ( d d r 3 ) r e s e t # c o m m a n d b a o d t r t t t c k s r x t m i n = 2 0 0 s t = 5 0 0 s t d l l k v a l i d v a l i d v a l i d v a l i d s t a t i c l o w i n c a s e r t t _ n o m i s e n a b l e d a t t i m e t g , o t h e r w i s e s t a t i c h i g h o r l o w * 1 z q c l m r s * 1 m r s m r s m r s m r 2 m r 3 m r 1 m r 0 t i s t i s t i s t i s t x p r t m r d t m r d t m r d t m o d t z q i n i t c k e v d d , v d d q ( d d r 3 l ) t m i n = 1 0 n s t m i n = 1 0 n s t m i n = 1 0 n s
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 159 - 12. package specificatio n package outline w bga 78 ( 8 x1 0.5 mm 2 , ball pitch: 0.8mm, ? =0.45mm ) t h e w i n d o w - s i d e e n c a p s u l a n t a b c d f e g h j k l m n 7 8 x b s o l d e r b a l l d i a m e t e r r e f e r s . t o p o s t r e f l o w c o n d i t i o n . e p i n a 1 i n d e x a e d e e 1 2 3 7 8 9 p i n a 1 i n d e x e 1 d 1 c c c c c c b b b / / a b 4 x c a a a s y m b o l d i m e n s i o n i n m m m i n . n o m . m a x . a a 1 b d e d 1 e 1 e e e d a a a b b b c c c d d d - - - - - - - - - - - - - - - - - - 0 . 1 5 0 . 1 0 0 . 2 0 - - - - - - 0 . 1 5 0 . 8 0 b s c . 0 . 8 0 b s c . 6 . 4 0 b s c . 9 . 6 0 b s c . 1 . 2 0 0 . 4 0 0 . 5 0 1 0 . 6 0 8 . 1 0 8 . 0 0 1 0 . 5 0 7 . 9 0 1 0 . 4 0 0 . 4 0 0 . 2 5 - - - 0 . 4 5 - - - - - - a c m d d d b e e e - - - - - - 0 . 0 8 c m e e e d 4 5 6 d i m e n s i o n i n i n c h m i n . n o m . m a x . - - - - - - - - - - - - - - - - - - - - - - - - 0 . 0 3 1 5 b s c . 0 . 0 3 1 5 b s c . 0 . 2 5 1 9 b s c . 0 . 3 7 8 0 b s c . 0 . 0 4 7 2 - - - - - - - - - - - - - - - 0 . 0 1 5 7 0 . 0 1 9 7 0 . 4 1 7 3 0 . 3 1 8 9 0 . 0 0 9 8 0 . 0 1 5 7 0 . 4 0 9 4 0 . 3 1 1 0 - - - 0 . 4 1 3 4 0 . 3 1 5 0 0 . 0 0 5 9 0 . 0 7 8 0 0 . 0 0 3 9 0 . 0 0 5 9 0 . 0 0 3 1 b a l l l a n d b a l l o p e n i n g n o t e : 1 . b a l l l a n d : 0 . 5 m m , b a l l o p e n i n g : 0 . 4 m m , p c b b a l l l a n d s u g g e s t e d 0 . 4 m m 1 a 1
w632gu8kb publication release date: jan. 20 , 2015 revision: a05 - 160 - 13. rev i sion history version date page description a 0 1 jun. 0 4 , 2013 all initial formally data shee t a02 dec. 24, 2013 11 added block diagram 7, 17 133~135 added cl = 7, cwl = 6 support for ddr3l - 1600 and ddr3l 1333 speed bins a03 nov. 1 1 , 2014 5~7, 98, 121, 131, 133, 134, 136~139 removed 12a, 12k, 15a and 15k grade parts 5, 151, 152 added b ackward c ompatible to 1.5v ddr3 sdram v dd /v ddq r equirements a04 dec. 08, 2014 6, 98 commercial operating temperature range change from 0c t case 8 5c to 0c t case 9 5c a05 jan. 20 , 2015 5~7, 17, 22, 80, 98, 100, 102, 103, 105, 106, 111, 119~121, 131, 135~140, 147, 148, 150, 155, 156 added ddr3l - 1866 - 1 1 grade parts important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environme ntal damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

▲Up To Search▲

Price & Availability of W632GU8KB15I

	To Download W632GU8KB15I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .